arm64: dts: rockchip: rk3588s: Fix PCIe node

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iac3f0af7d8911cf188cc29788b4777a446536361
This commit is contained in:
Shawn Lin
2023-04-07 17:16:56 +08:00
parent aea0f350c4
commit 7439ad8700

View File

@@ -4771,13 +4771,13 @@
num-lanes = <1>;
phys = <&combphy2_psu PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
ranges = <0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
reg = <0x0 0xfe180000 0x0 0x10000>,
<0xa 0x40c00000 0x0 0x400000>;
reg-names = "pcie-apb", "pcie-dbi";
<0xa 0x40c00000 0x0 0x400000>,
<0x0 0xf3000000 0x0 0x100000>;
reg-names = "pcie-apb", "pcie-dbi", "config";
resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
reset-names = "pcie", "periph";
rockchip,pipe-grf = <&php_grf>;
@@ -4825,13 +4825,13 @@
num-lanes = <1>;
phys = <&combphy0_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
ranges = <0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
reg = <0x0 0xfe190000 0x0 0x10000>,
<0xa 0x41000000 0x0 0x400000>;
reg-names = "pcie-apb", "pcie-dbi";
<0xa 0x41000000 0x0 0x400000>,
<0x0 0xf4000000 0x0 0x100000>;
reg-names = "pcie-apb", "pcie-dbi", "config";
resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
reset-names = "pcie", "periph";
rockchip,pipe-grf = <&php_grf>;