shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 11:50:43 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: sm1: add sm1 special clk [1/1]

Browse Source 
PD#SWPL-5407

Problem:
not include sm1 special defined clk

Solution:
add this clk

Verify:
sm1_skt

Change-Id: Iaf20aebe377d077d95eb053f7eea99473e3ac45d
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
This commit is contained in:
Shunzhou Jiang
2019-03-22 19:09:42 +08:00
committed by Luan Yuan
parent 20114ecec2
commit 74dcf06299
5 changed files with 86 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/amlogic/clk/g12a/g12a.c
View File

@@ -175,8 +175,8 @@ static struct meson_clk_pll g12a_hifi_pll = {
.shift = 16,
.width = 2,
},
.rate_table = g12a_pll_rate_table,
.rate_count = ARRAY_SIZE(g12a_pll_rate_table),
.rate_table = g12a_hifi_pll_rate_table,
.rate_count = ARRAY_SIZE(g12a_hifi_pll_rate_table),
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "hifi_pll",

4
drivers/amlogic/clk/g12a/g12a.h
View File

@@ -221,4 +221,8 @@ static const struct pll_rate_table g12a_pcie_pll_rate_table[] = {
PLL_RATE(100000000, 150, 0, 9),
{ /* sentinel */ },
};
static const struct pll_rate_table g12a_hifi_pll_rate_table[] = {
PLL_RATE(666000000ULL, 222, 1, 3), /*DCO=5328M*/
};
#endif /* __G12A_H */

113
drivers/amlogic/clk/g12a/g12a_clk-pll.c
View File

@@ -64,19 +64,6 @@
#define G12A_PCIE_PLL_CNTL5 0x68000048
#define G12A_PCIE_PLL_CNTL5_ 0x68000068
#define G12B_PCIE_PLL_CNTL0_0 0x28060464
#define G12B_PCIE_PLL_CNTL0_1 0x38060464
#define G12B_PCIE_PLL_CNTL0_2 0x3c060464
#define G12B_PCIE_PLL_CNTL0_3 0x1c060464
#define G12B_PCIE_PLL_CNTL1 0x00000000
#define G12B_PCIE_PLL_CNTL2 0x00001100
#define G12B_PCIE_PLL_CNTL2_ 0x00001000
#define G12B_PCIE_PLL_CNTL3 0x10058e00
#define G12B_PCIE_PLL_CNTL4 0x000100c0
#define G12B_PCIE_PLL_CNTL4_ 0x008100c0
#define G12B_PCIE_PLL_CNTL5 0x68000048
#define G12B_PCIE_PLL_CNTL5_ 0x68000068
#define G12A_SYS_PLL_CNTL1 0x00000000
#define G12A_SYS_PLL_CNTL2 0x00000000
#define G12A_SYS_PLL_CNTL3 0x48681c00
@@ -89,7 +76,7 @@
#define G12A_SYS1_PLL_CNTL4 0x88770290
#define G12A_SYS1_PLL_CNTL5 0x39272000
#define G12A_GP0_PLL_CNTL1 0x00000000
#define G12A_GP0_PLL_CNTL1 0x00007800
#define G12A_GP0_PLL_CNTL2 0x00000000
#define G12A_GP0_PLL_CNTL3 0x48681c00
#define G12A_GP0_PLL_CNTL4 0x33771290
@@ -271,66 +258,34 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
if ((get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) ||
((get_cpu_type() == MESON_CPU_MAJOR_ID_SM1))) {
writel(G12A_PCIE_PLL_CNTL0_0,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_1,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5*4));
udelay(20);
writel(G12A_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4*4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(G12A_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_3,
cntlbase + (unsigned long)(0*4));
udelay(10);
writel(G12A_PCIE_PLL_CNTL2_,
cntlbase + (unsigned long)(2*4));
} else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B) {
writel(G12B_PCIE_PLL_CNTL0_0,
cntlbase + (unsigned long)(0*4));
writel(G12B_PCIE_PLL_CNTL0_1,
cntlbase + (unsigned long)(0*4));
writel(G12B_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12B_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12B_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12B_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12B_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12B_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5*4));
udelay(20);
writel(G12B_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4*4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(G12B_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0*4));
writel(G12B_PCIE_PLL_CNTL0_3,
cntlbase + (unsigned long)(0*4));
udelay(10);
writel(G12B_PCIE_PLL_CNTL2_,
cntlbase + (unsigned long)(2*4));
}
writel(G12A_PCIE_PLL_CNTL0_0,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_1,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5*4));
udelay(20);
writel(G12A_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4*4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(G12A_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_3,
cntlbase + (unsigned long)(0*4));
udelay(10);
writel(G12A_PCIE_PLL_CNTL2_,
cntlbase + (unsigned long)(2*4));
goto OUT;
} else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
@@ -384,15 +339,15 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_GP0_PLL_CNTL1,
writel(G12A_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_GP0_PLL_CNTL2,
writel(G12A_HIFI_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_GP0_PLL_CNTL3,
writel(G12A_HIFI_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_GP0_PLL_CNTL4,
writel(G12A_HIFI_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_GP0_PLL_CNTL5,
writel(G12A_HIFI_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));

39
drivers/amlogic/clk/sm1/sm1.c
View File

@@ -176,7 +176,7 @@ static struct clk_mux sm1_dsu_pre_clk = {
static struct clk_mux sm1_dsu_clk = {
.reg = (void *)HHI_SYS_CPU_CLK_CNTL6,
.mask = 0x1,
.shift = 11,
.shift = 27,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "dsu_clk",
@@ -192,6 +192,24 @@ static struct meson_clk_pll *const sm1_clk_plls[] = {
&sm1_gp1_pll,
};
static MESON_GATE(sm1_csi_dig, HHI_GCLK_MPEG1, 18);
static MESON_GATE(sm1_nna, HHI_GCLK_MPEG1, 19);
static MESON_GATE(sm1_parser1, HHI_GCLK_MPEG1, 28);
static MESON_GATE(sm1_csi_host, HHI_GCLK_MPEG2, 16);
static MESON_GATE(sm1_csi_adpat, HHI_GCLK_MPEG2, 17);
static MESON_GATE(sm1_temp_sensor, HHI_GCLK_MPEG2, 22);
static MESON_GATE(sm1_csi_phy, HHI_GCLK_MPEG2, 29);
static struct clk_gate *sm1_clk_gates[] = {
&sm1_csi_dig,
&sm1_nna,
&sm1_parser1,
&sm1_csi_host,
&sm1_csi_adpat,
&sm1_temp_sensor,
&sm1_csi_phy,
};
static struct clk_hw *sm1_clk_hws[] = {
[CLKID_GP1_PLL - CLKID_SM1_ADD_BASE] = &sm1_gp1_pll.hw,
[CLKID_DSU_PRE_SRC0 - CLKID_SM1_ADD_BASE] =
@@ -211,6 +229,20 @@ static struct clk_hw *sm1_clk_hws[] = {
[CLKID_DSU_PRE_CLK - CLKID_SM1_ADD_BASE] =
&sm1_dsu_pre_clk.hw,
[CLKID_DSU_CLK - CLKID_SM1_ADD_BASE] = &sm1_dsu_clk.hw,
[CLKID_CSI_DIG_CLK - CLKID_SM1_ADD_BASE] =
&sm1_csi_dig.hw,
[CLKID_NNA_CLK - CLKID_SM1_ADD_BASE] =
&sm1_nna.hw,
[CLKID_PARSER1_CLK - CLKID_SM1_ADD_BASE] =
&sm1_parser1.hw,
[CLKID_CSI_HOST_CLK - CLKID_SM1_ADD_BASE] =
&sm1_csi_host.hw,
[CLKID_CSI_ADPAT_CLK - CLKID_SM1_ADD_BASE] =
&sm1_csi_adpat.hw,
[CLKID_TEMP_SENSOR_CLK - CLKID_SM1_ADD_BASE] =
&sm1_temp_sensor.hw,
[CLKID_CSI_PHY_CLK - CLKID_SM1_ADD_BASE] =
&sm1_csi_phy.hw,
};
static void __init sm1_clkc_init(struct device_node *np)
@@ -244,6 +276,11 @@ static void __init sm1_clkc_init(struct device_node *np)
+ (unsigned long)sm1_dsu_pre_clk.reg;
sm1_dsu_clk.reg = clk_base
+ (unsigned long)sm1_dsu_clk.reg;
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(sm1_clk_gates); i++)
sm1_clk_gates[i]->reg = clk_base +
(unsigned long)sm1_clk_gates[i]->reg;
if (!clks) {
clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL);
if (!clks) {

9
include/dt-bindings/clock/amlogic,g12a-clkc.h
View File

@@ -308,8 +308,15 @@
#define CLKID_DSU_PRE_POST_MUX (CLKID_SM1_ADD_BASE + 7)
#define CLKID_DSU_PRE_CLK (CLKID_SM1_ADD_BASE + 8)
#define CLKID_DSU_CLK (CLKID_SM1_ADD_BASE + 9)
#define CLKID_CSI_DIG_CLK (CLKID_SM1_ADD_BASE + 10)
#define CLKID_NNA_CLK (CLKID_SM1_ADD_BASE + 11)
#define CLKID_PARSER1_CLK (CLKID_SM1_ADD_BASE + 12)
#define CLKID_CSI_HOST_CLK (CLKID_SM1_ADD_BASE + 13)
#define CLKID_CSI_ADPAT_CLK (CLKID_SM1_ADD_BASE + 14)
#define CLKID_TEMP_SENSOR_CLK (CLKID_SM1_ADD_BASE + 15)
#define CLKID_CSI_PHY_CLK (CLKID_SM1_ADD_BASE + 16)
#define CLKID_AO_BASE (CLKID_SM1_ADD_BASE + 10)
#define CLKID_AO_BASE (CLKID_SM1_ADD_BASE + 17)
#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)