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vdin: amlogic: add vdin driver support

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PD#154260: vdin: amlogic: add vdin driver support

Merge from kernel 3.14.
Optimize and fix memset error.

Change-Id: I0707de5cb6313da4e1ff8a3a1e91dfb098234529
Signed-off-by: Bencheng Jing <bencheng.jing@amlogic.com>
This commit is contained in:
Bencheng Jing
2017-11-28 13:00:01 +08:00
committed by Bo Yang
parent 878e0f00be
commit 7556ba8a7e
20 changed files with 4392 additions and 2407 deletions
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277
drivers/amlogic/media/vin/tvin/tvin_format_table.c
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@@ -327,6 +327,10 @@ const char *tvin_sig_fmt_str(enum tvin_sig_fmt_e fmt)
/* HDMI Formats */
case TVIN_SIG_FMT_HDMI_640X480P_60HZ:
return "TVIN_SIG_FMT_HDMI_640x480P_60Hz";
case TVIN_SIG_FMT_HDMI_640X480P_72HZ:
return "TVIN_SIG_FMT_HDMI_640x480P_72Hz";
case TVIN_SIG_FMT_HDMI_640X480P_75HZ:
return "TVIN_SIG_FMT_HDMI_720x480P_75Hz";
case TVIN_SIG_FMT_HDMI_720X480P_60HZ:
return "TVIN_SIG_FMT_HDMI_720x480P_60Hz";
case TVIN_SIG_FMT_HDMI_1280X720P_60HZ:
@@ -497,6 +501,8 @@ const char *tvin_sig_fmt_str(enum tvin_sig_fmt_e fmt)
return "TVIN_SIG_FMT_CVBS_PAL_CN";
case TVIN_SIG_FMT_CVBS_SECAM:
return "TVIN_SIG_FMT_CVBS_SECAM";
case TVIN_SIG_FMT_CVBS_NTSC_50:
return "TVIN_SIG_FMT_CVBS_NTSC_50";
/* 656 Formats */
case TVIN_SIG_FMT_BT656IN_576I_50HZ:
return "TVIN_SIG_FMT_BT656IN_576I";
@@ -550,19 +556,19 @@ const struct tvin_format_s *tvin_get_fmt_info(enum tvin_sig_fmt_e fmt)
return NULL;
/* we also can find format table through port */
/*
* if(port != TVIN_PORT_NULL)
* {
* if ((port >= TVIN_PORT_VGA0) && (port < TVIN_PORT_VGA7))
* return &tvin_vga_fmt_tbl[fmt-TVIN_SIG_FMT_VGA_512X384P_60HZ_D147];
* else if ((port >= TVIN_PORT_COMP0) && (port < TVIN_PORT_COMP7))
* return &tvin_comp_fmt_tbl[fmt-TVIN_SIG_FMT_COMP_480P_60HZ_D000];
* else if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_SVIDEO7))
* return &tvin_cvbs_fmt_tbl[fmt-TVIN_SIG_FMT_CVBS_NTSC_M];
* else if ((port >= TVIN_PORT_HDMI0) && (port <= TVIN_PORT_HDMI7))
* return &tvin_hdmi_fmt_tbl[fmt-TVIN_SIG_FMT_HDMI_640X480P_60HZ];
* else if ((port >= TVIN_PORT_BT656) && (port <= TVIN_PORT_CAMERA))
* return &tvin_bt601_fmt_tbl[fmt-TVIN_SIG_FMT_BT656IN_576I_50HZ];
* }
if (port != TVIN_PORT_NULL)
{
if ((port >= TVIN_PORT_VGA0) && (port < TVIN_PORT_VGA7))
return &tvin_vga_fmt_tbl[fmt-TVIN_SIG_FMT_VGA_512X384P_60HZ_D147];
else if ((port >= TVIN_PORT_COMP0) && (port < TVIN_PORT_COMP7))
return &tvin_comp_fmt_tbl[fmt-TVIN_SIG_FMT_COMP_480P_60HZ_D000];
else if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_SVIDEO7))
return &tvin_cvbs_fmt_tbl[fmt-TVIN_SIG_FMT_CVBS_NTSC_M];
else if ((port >= TVIN_PORT_HDMI0) && (port <= TVIN_PORT_HDMI7))
return &tvin_hdmi_fmt_tbl[fmt-TVIN_SIG_FMT_HDMI_640X480P_60HZ];
else if ((port >= TVIN_PORT_BT656) && (port <= TVIN_PORT_CAMERA))
return &tvin_bt601_fmt_tbl[fmt-TVIN_SIG_FMT_BT656IN_576I_50HZ];
}
*/
}
EXPORT_SYMBOL(tvin_get_fmt_info);
@@ -570,10 +576,10 @@ EXPORT_SYMBOL(tvin_get_fmt_info);
const struct tvin_format_s tvin_vga_fmt_tbl[TVIN_SIG_FMT_VGA_MAX -
TVIN_SIG_FMT_VGA_512X384P_60HZ_D147 + 1] = {
/* H_Active V_Active H_cnt Hcnt_offset Vcnt_offset Hs_cnt Hscnt_offset
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
{/* TVIN_SIG_FMT_VGA_512X384P_60D147, */
512, 384, 0, 10, 10, 49, 10,
640, 407, 16, 32, 80, 1, 3,
@@ -1231,10 +1237,10 @@ EXPORT_SYMBOL(tvin_vga_fmt_tbl);
const struct tvin_format_s tvin_comp_fmt_tbl[TVIN_SIG_FMT_COMP_MAX -
TVIN_SIG_FMT_COMP_480P_60HZ_D000 + 1] = {
/* H_Active V_Active H_cnt Hcnt_offset Vcnt_offset Hs_cnt Hscnt_offset
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
{/* TVIN_SIG_FMT_COMPONENT_480P_60D000, */
1440, 480, 762, 20, 20, 55, 10,
1716, 525, 32, 124, 120, 9, 6,
@@ -1355,10 +1361,10 @@ EXPORT_SYMBOL(tvin_comp_fmt_tbl);
const struct tvin_format_s tvin_comp_fmt_tbl[TVIN_SIG_FMT_COMP_MAX -
TVIN_SIG_FMT_COMP_480P_60HZ_D000 + 1] = {
/* H_Active V_Active H_cnt Hcnt_offset Vcnt_offset Hs_cnt Hscnt_offset
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
{ /* TVIN_SIG_FMT_COMPONENT_480P_60D000, */
720, 480, 762, 20, 20, 55, 10,
858, 525, 16, 62, 60, 9, 6,
@@ -1946,6 +1952,18 @@ const struct tvin_format_s tvin_hdmi_fmt_tbl[TVIN_SIG_FMT_HDMI_MAX -
39, TVIN_SYNC_POL_NEGATIVE, TVIN_SYNC_POL_NEGATIVE,
TVIN_SCAN_MODE_PROGRESSIVE, 5400, 0, 0, 1920
},
{/* TVIN_SIG_FMT_HDMI_640x480P_72Hz, */
640, 480, 0, 10, 10, 0, 10,
800, 525, 16, 96, 48, 10, 2,
33, TVIN_SYNC_POL_NEGATIVE, TVIN_SYNC_POL_NEGATIVE,
TVIN_SCAN_MODE_PROGRESSIVE, 3000, 0, 0, 1333
},
{/* TVIN_SIG_FMT_HDMI_640x480P_75Hz, */
640, 480, 0, 10, 10, 0, 10,
800, 525, 16, 96, 48, 10, 2,
33, TVIN_SYNC_POL_NEGATIVE, TVIN_SYNC_POL_NEGATIVE,
TVIN_SCAN_MODE_PROGRESSIVE, 3125, 0, 0, 1066
},
{/* TVIN_SIG_FMT_HDMI_MAX,//227 */
0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@@ -1958,10 +1976,10 @@ EXPORT_SYMBOL(tvin_hdmi_fmt_tbl);
const struct tvin_format_s tvin_cvbs_fmt_tbl[TVIN_SIG_FMT_CVBS_MAX -
TVIN_SIG_FMT_CVBS_NTSC_M + 1] = {
/* H_Active V_Active H_cnt Hcnt_offset Vcnt_offset Hs_cnt Hscnt_offset
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
* H_Total V_Total Hs_Front Hs_Width Hs_bp Vs_Front Vs_Width
* Vs_bp Hs_Polarity Vs_Polarity
* Scan_Mode Pixel_Clk(Khz/10) VBIs VBIe duration
*/
{ /* TVIN_SIG_FMT_CVBS_NTSC_M, */
720, 240, 0, 0, 0, 0, 0,
@@ -2005,6 +2023,12 @@ const struct tvin_format_s tvin_cvbs_fmt_tbl[TVIN_SIG_FMT_CVBS_MAX -
0, TVIN_SYNC_POL_NEGATIVE, TVIN_SYNC_POL_NEGATIVE,
TVIN_SCAN_MODE_INTERLACED, 1350, 0, 0, 1920
},
{ /* TVIN_SIG_FMT_CVBS_NTSC_50, */
720, 240, 0, 0, 0, 0, 0,
858, 263, 16, 62, 0, 4, 3,
0, TVIN_SYNC_POL_NEGATIVE, TVIN_SYNC_POL_NEGATIVE,
TVIN_SCAN_MODE_INTERLACED, 1350, 0, 0, 1600
},
{ /* TVIN_SIG_FMT_CVBS_MAX, */
0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@@ -4303,54 +4327,54 @@ EXPORT_SYMBOL(adc_cvbs_table);
#define r1f6 (unsigned char)((CVD2_HSYNC_DTO_SECAM >> 0)&0x000000ff)
/* 00~3f */
const unsigned char cvd_part1_table[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned char cvd_part1_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][CVD_PART1_REG_NUM] = {
{
0x00, 0x08, 0x43, 0x10, 0xdd, 0x32, 0x80, 0x4e, 0x7b, 0x1c, 0x78,
0x00, 0x90, 0x00, 0x06, 0x00, 0x0a, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r180, r190, r1a0, r1b0, r1c0, r1d0, r1e0, r1f0, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x32, 0x46, 0x82, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
0x32, 0x46, 0x82, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_NTSC_M, */
{
0x00, 0x01, 0x43, 0x82, 0xdd, 0x32, 0x80, 0x40, 0x7e, 0x20, 0x80,
0x00, 0x8a, 0x00, 0x06, 0x00, 0x37, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r181, r191, r1a1, r1b1, r1c1, r1d1, r1e1, r1f1, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x32, 0x46, 0x7a, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
0x32, 0x46, 0x7a, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_NTSC_443, */
{
0x32, 0x04, 0x43, 0x12, 0xdd, 0x32, 0x80, 0x03, 0x7d, 0x20, 0x78,
0x00, 0x90, 0x00, 0x06, 0x00, 0x37, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r182, r192, r1a2, r1b2, r1c2, r1d2, r1e2, r1f2, 0x3e,
0x3e, 0x00, 0x80, 0xe7, 0x42, 0x6d, 0x5a, 0x1d, 0xb9, 0xd6, 0x4e,
0x32, 0x46, 0x8c, 0x50, 0x2a, 0xc0, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x8a, 0x2e, 0x00, 0x0d, 0x00, 0x00, 0x01
0x32, 0x46, 0x8c, 0x50, 0x2a, 0xc0, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x2e, 0x00, 0x0d, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_PAL_I, */
{
0x04, 0x01, 0x43, 0x12, 0xdd, 0x32, 0x80, 0x00, 0x7d, 0x20, 0x80,
0x00, 0x8a, 0x00, 0x06, 0x00, 0x37, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r183, r193, r1a3, r1b3, r1c3, r1d3, r1e3, r1f3, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x32, 0x46, 0x82, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
0x32, 0x46, 0x82, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_PAL_M, */
{
0x04, 0x00, 0x43, 0x02, 0xdd, 0x32, 0x80, 0x00, 0x80, 0x20, 0x80,
0x00, 0x67, 0x01, 0x06, 0x00, 0x37, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r184, r194, r1a4, r1b4, r1c4, r1d4, r1e4, r1f4, 0x3e,
0xf6, 0x0b, r184, r194, r1a4, r1b4, r1c4, r1d4, r1e4, r1f4, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x32, 0x46, 0x84, 0x50, 0x2a, 0x61, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
0x32, 0x46, 0x84, 0x50, 0x2a, 0x61, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_PAL_60, */
{
0x36, 0x01, 0x43, 0x12, 0xdd, 0x32, 0x80, 0x00, 0x7d, 0x31, 0x80,
0x00, 0x8a, 0x00, 0x06, 0x00, 0x37, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r185, r195, r1a5, r1b5, r1c5, r1d5, r1e5, r1f5, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x32, 0x46, 0x8a, 0x50, 0x2d, 0xc1, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x32, 0x46, 0x8a, 0x50, 0x2d, 0xc1, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_PAL_CN, */
{
@@ -4358,9 +4382,17 @@ const unsigned char cvd_part1_table[TVIN_SIG_FMT_CVBS_SECAM -
0x00, 0xc8, 0x00, 0x06, 0x00, 0x37, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r186, r196, r1a6, r1b6, r1c6, r1d6, r1e6, r1f6, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x3c, 0x6e, 0x76, 0x58, 0x29, 0xbf, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
0x3c, 0x6e, 0x76, 0x58, 0x29, 0xbf, 0x70, 0x0e, 0x78, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x00, 0x08, 0x43, 0x10, 0xdd, 0x32, 0x80, 0x4e, 0x7b, 0x1c, 0x78,
0x00, 0x90, 0x00, 0x06, 0x00, 0x0a, 0x09, 0x10, 0xb4, 0x80, 0x20,
0xf6, 0x0d, r180, r190, r1a0, r1b0, r1c0, r1d0, r1e0, r1f0, 0x3e,
0x3e, 0x00, 0x80, 0xf3, 0x3e, 0x6d, 0x5a, 0x07, 0x29, 0xd6, 0x4e,
0x32, 0x46, 0x82, 0x50, 0x22, 0x61, 0x70, 0x0e, 0x6c, 0x10, 0x00,
0x23, 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(cvd_part1_table);
@@ -4390,7 +4422,7 @@ EXPORT_SYMBOL(cvd_part1_table);
#define r_f8 0x00
#define r_ff 0x00
/* 70~ff */
const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][CVD_PART2_REG_NUM] = {
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -4400,7 +4432,7 @@ const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_SECAM -
r_9c, r_9d, r_9e, r_9f, 0xf2, 0x0b, 0x00, 0x00, 0x08, 0x08, 0x00,
0x00, 0x00, 0x00, 0x16, 0x0f, 0xc1, r_ad, 0xcf, 0x0f, 0x30, 0x2d,
0x04, 0x0b, 0x23, 0xa2, 0x02, 0x00, 0x00, r_b9, 0x24, 0x5f, 0x00,
0x25, 0x55, r_bf, 0x14, r_c1, 0x40, 0xc0, 0xfe, 0x90, 0x7d, 0xf0,
0x25, 0x55, r_bf, 0x14, r_c1, 0x40, 0xc0, 0xfe, 0x90, 0x00, 0xf0,
0x01, 0x50, 0x60, 0x90, 0xe3, 0x0c, 0x23, r_cf, 0xc0, 0x08, 0x10,
0x10, 0x0a, 0x00, 0x0d, 0x00, 0x00, 0x05, 0x00, 0x05, 0x50, r_dd,
0x08, r_df, 0x00, 0x00, 0x00, 0x00, 0x6e, 0x50, 0x00, 0x00, 0x04,
@@ -4414,7 +4446,7 @@ const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_SECAM -
0x00, 0x00, 0x00, r_89, 0x0a, 0x11, r_8c, 0x0a, 0x00, 0xe2, 0x00,
0x00, 0x01, 0x00, 0x08, 0x00, 0x00, r_97, r_98, r_99, r_9a, r_9b,
r_9c, r_9d, r_9e, r_9f, 0xf2, 0x0b, 0x00, 0x00, 0x08, 0x08, 0x00,
0x00, 0x00, 0x00, 0x16, 0x0f, 0xc1, r_ad, 0xcf, 0x8c, 0xe0, 0x2d,
0x00, 0x00, 0x00, 0x16, 0x0f, 0xc1, r_ad, 0xcf, 0x8c, 0x3a, 0xf3,
0x8, 0x03, 0x24, 0xa2, 0x02, 0x00, 0x00, r_b9, 0x24, 0x5f, 0x00,
0x25, 0x55, r_bf, 0x17, r_c1, 0x40, 0xc0, 0xfe, 0x90, 0x00, 0x00,
0x01, 0x50, 0x62, 0x90, 0xe3, 0x0c, 0x23, r_cf, 0xc0, 0x08, 0x10,
@@ -4504,11 +4536,27 @@ const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_SECAM -
0xe4, r_f5, r_f6, r_f7, r_f8, 0x01, 0x00, 0x50, 0x6e, 0x05, 0xdc,
r_ff
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x04, r_81, 0x42, 0x6f, 0x03, 0x00,
0x00, 0x00, 0x00, r_89, 0x0a, 0x11, r_8c, 0x0a, 0x00, 0xe2, 0x00,
0x00, 0x01, 0x08, 0x08, 0x00, 0x00, r_97, r_98, r_99, r_9a, r_9b,
r_9c, r_9d, r_9e, r_9f, 0xf2, 0x0b, 0x00, 0x00, 0x08, 0x08, 0x00,
0x00, 0x00, 0x00, 0x16, 0x0f, 0xc1, r_ad, 0xcf, 0x0f, 0x30, 0x2d,
0x04, 0x0b, 0x23, 0xa2, 0x02, 0x00, 0x00, r_b9, 0x24, 0x5f, 0x00,
0x25, 0x55, r_bf, 0x14, r_c1, 0x40, 0xc0, 0xfe, 0x90, 0x7d, 0xf0,
0x01, 0x50, 0x60, 0x90, 0xe3, 0x0c, 0x23, r_cf, 0xc0, 0x08, 0x10,
0x10, 0x0a, 0x00, 0x0d, 0x00, 0x00, 0x05, 0x00, 0x05, 0x50, r_dd,
0x08, r_df, 0x00, 0x00, 0x00, 0x00, 0x6e, 0x50, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, r_ef, 0x20, 0x40, 0x32, 0x46,
0xe4, r_f5, r_f6, r_f7, r_f8, 0x01, 0x00, 0x32, 0x50, 0x1c, 0x00,
r_ff
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(cvd_part2_table);
/* 0x87, 0x93, 0x94, 0x95, 0x96, 0xe6, 0xfa */
const unsigned int cvd_part3_table[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned int cvd_part3_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][CVD_PART3_REG_NUM] = {
{
0x00000000, 0x98000000, 0x0000FF08, 0x00000000, 0x8b000000,
@@ -4538,11 +4586,15 @@ const unsigned int cvd_part3_table[TVIN_SIG_FMT_CVBS_SECAM -
0x00000000, 0x98000000, 0x0000FF08, 0x00000000, 0x8b000000,
0x0000008c, 0x00000080
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x00000000, 0x98000000, 0x0000FF08, 0x00000000, 0x8b000000,
0x0000008c, 0x00000000
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(cvd_part3_table);
const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][ACD_REG_NUM+1] = {
{
0x10101002, 0x0, 0x7f00e110, 0x08881e18, 0xb36d1858,
@@ -4620,7 +4672,7 @@ const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
0x00000000, 0x021000ff, 0x80688030, 0x81f11111, 0x81f85852,
0x00680068, 0x0487101c, 0x00000003, 0x00000000, 0x00012002,
0x00028040, 0x00000000, 0x10000000, 0x7f1ff000, 0x00000000,
0x10101040, 0x40404040, 0x80000f5c, 0xff000000, 0x00000000,
0x10101040, 0x40404040, 0x00000000, 0xff000000, 0x00000000,
0x00000000, 0x00ffffff, 0x00000fff, 0x80000000, 0x00000000,
0x00000000, 0xc00833da, 0xba5b0391, 0x000ae232, 0x00000000,
0xf0080610, 0x60001808, 0x00009410, 0x00000003, 0x00000000,
@@ -4833,7 +4885,7 @@ const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
0x00000000, 0x66666442, 0x20e00044, 0x00000101, 0x00000000,
0x80010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x08205040, 0x0050c0c0,
0x00000000, 0x020f00ff, 0x80808020, 0x81f11111, 0x81f24742,
0xc9000418, 0x020f00ff, 0x80808020, 0x81f11111, 0x81f24742,
0x80200020, 0x03000000, 0x00000003, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x10000000, 0x7f1ff000, 0x00000000,
0x40404040, 0x40404040, 0x00000000, 0xff000000, 0x00000000,
@@ -4924,10 +4976,65 @@ const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
0x90000fff,
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x10101002, 0x0, 0x7f00e110, 0x08881e18, 0xb36d1858,
0x00007612, 0x00000000, 0x77444444, 0x20e000fe, 0x00000101,
0x0c000100, 0x80010909, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x1010403c, 0x44060606, 0x08080044, 0x00080808,
0xc006844b, 0x40200808, 0x44440044, 0x00008c80, 0xf0008888,
0xa0461006, 0x70ff0404, 0x0400208c, 0x48484848, 0x00004444,
0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x02020000,
0x0209c832, 0x00000000, 0xeafb4e8e, 0x2, 0xe7f14e8e,
0x00140008, 0x20070000, 0x0036e946, 0x00001001, 0x10e0474f,
0x00880358, 0x00130103, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000050, 0x00000000, 0x000003ff, 0x00000000,
0x00000000, 0x00000000, 0x0004cfb0, 0x00000000, 0x030000f0,
0x0000000a, 0x0000164e, 0x0003d55e, 0x000000f0, 0x00000001,
0x00000400, 0x7f00e110, 0x08881e18, 0xb36d1858, 0x00007612,
0x00000000, 0x77444444, 0x20e000fe, 0x00000101, 0x0c000100,
0x80010909, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x50502070, 0x401020,
0xd9801c0c, 0x21f00ff, 0x8080801c, 0x81f11111, 0x81f85852,
0x00680068, 0x0487101c, 0x00000003, 0x00000000, 0x00012002,
0x00028040, 0x00000000, 0x08000000, 0x7f1ff000, 0x00000000,
0x10101040, 0x40404040, 0x80000f5c, 0xff000000, 0x00000000,
0x00000000, 0x00ffffff, 0x00000fff, 0x80000000, 0x00000000,
0x00000000, 0xa00833da, 0xba5b0391, 0x000ae232, 0x00000000,
0xf0080610, 0x3000180a, 0x9c10, 0x00000182, 0x00000000,
0x81000002, 0x83020010, 0x000121ff, 0x000c0340, 0x40305c1c,
0x00d63650, 0x00c184af, 0x00c1837f, 0x00c18329, 0x01000100,
0x43062222, 0x75777577, 0x00000000, 0x00000718, 0x9968edd6,
0x3553fab0, 0x026f2865, 0x00018018, 0x00040010, 0x00000000,
0x00000000, 0x002468b5, 0x002fa63a, 0x0143a740, 0x00032864,
0x00001b10, 0x0371d249, 0x0003ebde, 0x00032864, 0x00001b10,
0x0371d249, 0x0003ebde, 0X00032864, 0x00001b10, 0x0371d249,
0x0003ebde, 0x00032864, 0x00001b10, 0x0371d249, 0x0003ebde,
0x3f000100, 0x0fff0000, 0x3f000100, 0x0fff0000, 0x00000000,
0x00000000, 0x00000000, 0x90000fff, 0x3f000100, 0x0fff0000,
0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff, 0x00000000,
0x90000fff, 0x3f000100, 0x0fff0000, 0x3f000100, 0x0fff0000,
0x00000000, 0x90000fff, 0x00000000, 0x90000fff, 0x3f000100,
0x0fff0000, 0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff,
0x00000000, 0x90000fff, 0x00c1837e, 0x01000100, 0x43062222,
0x75777577, 0x00000000, 0x00192718, 0x9968edd6, 0x3553fab0,
0x026f2865, 0x00018018, 0x00040010, 0x00000000, 0x00000000,
0x00247e04, 0x002fa52a, 0x0143a2ef, 0x000327bf, 0x00001b03,
0x0371b470, 0x0003f28b, 0x000327bf, 0x00001b03, 0x0371b470,
0x0003f28b, 0x000327bf, 0x00001b03, 0x0371b470, 0x0003f28b,
0x000327bf, 0x00001b03, 0x0371b470, 0x00000003, 0x3f000100,
0x0fff0000, 0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff,
0x00000000, 0x90000fff, 0x3f000100, 0x0fff0000, 0x3f000100,
0x0fff0000, 0x00000000, 0x90000fff, 0x00000000, 0x90000fff,
0x3f000100, 0x0fff0000, 0x0f000100, 0x0fff0000, 0x00000000,
0x90000fff, 0x00000000, 0x90000fff, 0x3f000100, 0x0fff0000,
0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff, 0x00000000,
0x90000fff,
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(cvbs_acd_table);
const unsigned int rf_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned int rf_acd_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M+1][ACD_REG_NUM+1] = {
{
0x10101002, 0x0, 0x7f00e110, 0x08881e18, 0xb36d1858,
@@ -5221,7 +5328,7 @@ const unsigned int rf_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
0x00000000, 0x66666442, 0x20e00044, 0x00000101, 0x00000000,
0x80010101, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x08205040, 0x0050c0c0,
0x00000000, 0x020f00ff, 0x80808020, 0x81f11111, 0x81f24742,
0xc9000418, 0x020f00ff, 0x80808020, 0x81f11111, 0x81f24742,
0x80200020, 0x03000000, 0x00000003, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x10000000, 0x7f1ff000, 0x00000000,
0x40404040, 0x40404040, 0x00000000, 0xff000000, 0x00000000,
@@ -5312,11 +5419,65 @@ const unsigned int rf_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff, 0x00000000,
0x90000fff,
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x10101002, 0x0, 0x7f00e110, 0x08881e18, 0xb36d1858,
0x00007612, 0x00000000, 0x77444444, 0x20e000fe, 0x00000101,
0x0c000100, 0x80010909, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x1010403c, 0x44060606, 0x08080044, 0x00080808,
0xc006844b, 0x40200808, 0x44440044, 0x00008c80, 0xf0008888,
0xa0461006, 0x70ff0404, 0x0400208c, 0x48484848, 0x00004444,
0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x02020000,
0x0209c832, 0x00000000, 0xeafb4e8e, 0x2, 0xe7f14e8e,
0x00140008, 0x20070000, 0x0036e946, 0x00001001, 0x10e0474f,
0x00880358, 0x00130103, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000050, 0x00000000, 0x000003ff, 0x00000000,
0x00000000, 0x00000000, 0x0004cfb0, 0x00000000, 0x030000f0,
0x0000000a, 0x0000164e, 0x0003d55e, 0x000000f0, 0x00000001,
0x00000400, 0x7f00e110, 0x08881e18, 0xb36d1858, 0x00007612,
0x00000000, 0x77444444, 0x20e000fe, 0x00000101, 0x0c000100,
0x80010909, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x50502070, 0x401020,
0xd9801c0c, 0x21f00ff, 0x8080801c, 0x81f11111, 0x81f85852,
0x00680068, 0x0487101c, 0x00000003, 0x00000000, 0x00012002,
0x00028040, 0x00000000, 0x08000000, 0x7f1ff000, 0x00000000,
0x10101040, 0x40404040, 0x80000f5c, 0xff000000, 0x00000000,
0x00000000, 0x00ffffff, 0x00000fff, 0x80000000, 0x00000000,
0x00000000, 0xa00833da, 0xba5b0391, 0x000ae232, 0x00000000,
0xf0080610, 0x3000180a, 0x9c10, 0x00000182, 0x00000000,
0x81000002, 0x83020010, 0x000121ff, 0x000c0340, 0x40305c1c,
0x00d63650, 0x00c184af, 0x00c1837f, 0x00c18329, 0x01000100,
0x43062222, 0x75777577, 0x00000000, 0x00000718, 0x9968edd6,
0x3553fab0, 0x026f2865, 0x00018018, 0x00040010, 0x00000000,
0x00000000, 0x002468b5, 0x002fa63a, 0x0143a740, 0x00032864,
0x00001b10, 0x0371d249, 0x0003ebde, 0x00032864, 0x00001b10,
0x0371d249, 0x0003ebde, 0X00032864, 0x00001b10, 0x0371d249,
0x0003ebde, 0x00032864, 0x00001b10, 0x0371d249, 0x0003ebde,
0x3f000100, 0x0fff0000, 0x3f000100, 0x0fff0000, 0x00000000,
0x00000000, 0x00000000, 0x90000fff, 0x3f000100, 0x0fff0000,
0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff, 0x00000000,
0x90000fff, 0x3f000100, 0x0fff0000, 0x3f000100, 0x0fff0000,
0x00000000, 0x90000fff, 0x00000000, 0x90000fff, 0x3f000100,
0x0fff0000, 0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff,
0x00000000, 0x90000fff, 0x00c1837e, 0x01000100, 0x43062222,
0x75777577, 0x00000000, 0x00192718, 0x9968edd6, 0x3553fab0,
0x026f2865, 0x00018018, 0x00040010, 0x00000000, 0x00000000,
0x00247e04, 0x002fa52a, 0x0143a2ef, 0x000327bf, 0x00001b03,
0x0371b470, 0x0003f28b, 0x000327bf, 0x00001b03, 0x0371b470,
0x0003f28b, 0x000327bf, 0x00001b03, 0x0371b470, 0x0003f28b,
0x000327bf, 0x00001b03, 0x0371b470, 0x00000003, 0x3f000100,
0x0fff0000, 0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff,
0x00000000, 0x90000fff, 0x3f000100, 0x0fff0000, 0x3f000100,
0x0fff0000, 0x00000000, 0x90000fff, 0x00000000, 0x90000fff,
0x3f000100, 0x0fff0000, 0x0f000100, 0x0fff0000, 0x00000000,
0x90000fff, 0x00000000, 0x90000fff, 0x3f000100, 0x0fff0000,
0x3f000100, 0x0fff0000, 0x00000000, 0x90000fff, 0x00000000,
0x90000fff
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(rf_acd_table);
/* 0x00-0x03 */
const unsigned char cvd_yc_reg_0x00_0x03[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned char cvd_yc_reg_0x00_0x03[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][4] = {
{
0x01, 0x08, 0x42, 0x22,
@@ -5339,11 +5500,14 @@ const unsigned char cvd_yc_reg_0x00_0x03[TVIN_SIG_FMT_CVBS_SECAM -
{
0x00, 0x08, 0x42, 0x22,
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x01, 0x08, 0x42, 0x22,
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(cvd_yc_reg_0x00_0x03);
/* 0x18-0x1f */
const unsigned char cvd_yc_reg_0x18_0x1f[TVIN_SIG_FMT_CVBS_SECAM -
const unsigned char cvd_yc_reg_0x18_0x1f[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][8] = {
{
0x21, 0xf0, 0x7c, 0x1f, 0x24, 0x00, 0x00, 0x00,
@@ -5366,6 +5530,9 @@ const unsigned char cvd_yc_reg_0x18_0x1f[TVIN_SIG_FMT_CVBS_SECAM -
{
0x28, 0xa3, 0x3b, 0xb2, 0x24, 0x00, 0x00, 0x00,
}, /* TVIN_SIG_FMT_CVBS_SECAM, */
{
0x21, 0xf0, 0x7c, 0x1f, 0x24, 0x00, 0x00, 0x00,
}, /* TVIN_SIG_FMT_CVBS_NTSC_50, */
};
EXPORT_SYMBOL(cvd_yc_reg_0x18_0x1f);

14
drivers/amlogic/media/vin/tvin/tvin_format_table.h
View File

@@ -40,22 +40,22 @@ extern const unsigned char adc_vga_table[TVIN_SIG_FMT_VGA_MAX -
extern const unsigned char adc_component_table[TVIN_SIG_FMT_COMP_MAX -
TVIN_SIG_FMT_COMP_480P_60HZ_D000][ADC_REG_NUM];
extern const unsigned char adc_cvbs_table[ADC_REG_NUM];
extern const unsigned char cvd_part1_table[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned char cvd_part1_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][CVD_PART1_REG_NUM];
extern const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned char cvd_part2_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][CVD_PART2_REG_NUM];
/* 0x87, 0x93, 0x94, 0x95, 0x96, 0xe6, 0xfa */
extern const unsigned int cvd_part3_table[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned int cvd_part3_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][CVD_PART3_REG_NUM];
extern const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned int cvbs_acd_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][ACD_REG_NUM+1];
extern const unsigned int rf_acd_table[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned int rf_acd_table[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][ACD_REG_NUM+1];
extern const unsigned char cvd_yc_reg_0x00_0x03[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned char cvd_yc_reg_0x00_0x03[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][4];
extern const unsigned char cvd_yc_reg_0x18_0x1f[TVIN_SIG_FMT_CVBS_SECAM -
extern const unsigned char cvd_yc_reg_0x18_0x1f[TVIN_SIG_FMT_CVBS_NTSC_50 -
TVIN_SIG_FMT_CVBS_NTSC_M + 1][8];

3
drivers/amlogic/media/vin/tvin/tvin_frontend.c
View File

@@ -54,7 +54,6 @@ int tvin_reg_frontend(struct tvin_frontend_s *fe)
{
ulong flags;
struct tvin_frontend_s *f, *t;
if (!strlen(fe->name) || !fe->dec_ops ||
!fe->dec_ops->support || !fe->sm_ops)
return -1;
@@ -138,7 +137,6 @@ static ssize_t frontend_name_show(struct class *cls,
{
size_t len = 0;
struct tvin_frontend_s *f = NULL;
list_for_each_entry(f, &head, list) {
len += sprintf(buf+len, "%s\n", f->name);
}
@@ -149,7 +147,6 @@ static CLASS_ATTR(frontend_names, 0444, frontend_name_show, NULL);
static int __init tvin_common_init(void)
{
int ret = 0;
tvcom_clsp = class_create(THIS_MODULE, CLASS_NAME);
if (!tvcom_clsp) {
pr_err("[tvin_com..]%s: create tvin common class error.\n",

53
drivers/amlogic/media/vin/tvin/tvin_global.h
View File

@@ -27,14 +27,20 @@
#ifdef TVBUS_REG_ADDR
#define R_APB_REG(reg) aml_read_reg32(TVBUS_REG_ADDR(reg))
#define W_APB_REG(reg, val) aml_write_reg32(TVBUS_REG_ADDR(reg), val)
#define R_VBI_APB_REG(reg) aml_read_reg32(TVBUS_REG_ADDR(reg))
#define W_VBI_APB_REG(reg, val) aml_write_reg32(TVBUS_REG_ADDR(reg), val)
#define R_APB_BIT(reg, start, len) \
aml_get_reg32_bits(TVBUS_REG_ADDR(reg), start, len)
#define W_APB_BIT(reg, val, start, len) \
aml_set_reg32_bits(TVBUS_REG_ADDR(reg), val, start, len)
#define W_VBI_APB_BIT(reg, val, start, len) \
aml_set_reg32_bits(TVBUS_REG_ADDR(reg), val, start, len)
#else
#if 1
extern int tvafe_reg_read(unsigned int reg, unsigned int *val);
extern int tvafe_reg_write(unsigned int reg, unsigned int val);
extern int tvafe_vbi_reg_read(unsigned int reg, unsigned int *val);
extern int tvafe_vbi_reg_write(unsigned int reg, unsigned int val);
extern int tvafe_hiu_reg_read(unsigned int reg, unsigned int *val);
extern int tvafe_hiu_reg_write(unsigned int reg, unsigned int val);
#else
@@ -55,7 +61,6 @@ static int tvafe_reg_write(unsigned int reg, unsigned int val)
static inline uint32_t R_APB_REG(uint32_t reg)
{
unsigned int val;
tvafe_reg_read(reg, &val);
return val;
}
@@ -66,6 +71,30 @@ static inline void W_APB_REG(uint32_t reg,
tvafe_reg_write(reg, val);
}
static inline uint32_t R_VBI_APB_REG(uint32_t reg)
{
unsigned int val = 0;
tvafe_vbi_reg_read(reg, &val);
return val;
}
static inline void W_VBI_APB_REG(uint32_t reg,
const uint32_t val)
{
tvafe_vbi_reg_write(reg, val);
}
static inline void W_VBI_APB_BIT(uint32_t reg,
const uint32_t value,
const uint32_t start,
const uint32_t len)
{
W_VBI_APB_REG(reg, ((R_VBI_APB_REG(reg) &
~(((1L << (len)) - 1) << (start))) |
(((value) & ((1L << (len)) - 1)) << (start))));
}
static inline void W_APB_BIT(uint32_t reg,
const uint32_t value,
const uint32_t start,
@@ -112,7 +141,6 @@ static inline uint32_t R_VCBUS_BIT(uint32_t reg,
static inline uint32_t R_HIU_REG(uint32_t reg)
{
unsigned int val;
tvafe_hiu_reg_read(reg, &val);
return val;
}
@@ -145,13 +173,13 @@ static inline uint32_t R_HIU_BIT(uint32_t reg,
}
/*
*#define R_APB_REG(reg) READ_APB_REG(reg)
*#define W_APB_REG(reg, val) WRITE_APB_REG(reg, val)
*#define R_APB_BIT(reg, start, len) \
* READ_APB_REG_BITS(reg, start, len)
*#define W_APB_BIT(reg, val, start, len) \
* WRITE_APB_REG_BITS(reg, val, start, len)
*/
#define R_APB_REG(reg) READ_APB_REG(reg)
#define W_APB_REG(reg, val) WRITE_APB_REG(reg, val)
#define R_APB_BIT(reg, start, len) \
READ_APB_REG_BITS(reg, start, len)
#define W_APB_BIT(reg, val, start, len) \
WRITE_APB_REG_BITS(reg, val, start, len)
*/
#endif
@@ -404,11 +432,18 @@ struct tvin_sig_property_s {
unsigned int he; /* for horizontal end cut window */
unsigned int vs; /* for vertical start cut window */
unsigned int ve; /* for vertical end cut window */
unsigned int pre_vs; /* for vertical start cut window */
unsigned int pre_ve; /* for vertical end cut window */
unsigned int pre_hs; /* for horizontal start cut window */
unsigned int pre_he; /* for horizontal end cut window */
unsigned int decimation_ratio; /* for decimation */
unsigned int colordepth; /* for color bit depth */
unsigned int vdin_hdr_Flag;
enum tvin_color_fmt_range_e color_fmt_range;
struct tvin_hdr_info_s hdr_info;
bool dolby_vision;/*is signal dolby version*/
uint8_t fps;
unsigned int skip_vf_num;/*skip pre vframe num*/
};
#define TVAFE_VF_POOL_SIZE 6 /* 8 */

620
drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c
View File

@@ -18,6 +18,10 @@
/* Standard Linux headers */
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/cma.h>
#include <linux/amlogic/media/codec_mm/codec_mm.h>
#include <linux/dma-contiguous.h>
/* Amlogic headers */
#include <linux/amlogic/media/vfm/vframe.h>
@@ -26,16 +30,34 @@
#include "../tvin_format_table.h"
#include "vdin_drv.h"
#include "vdin_canvas.h"
#include "vdin_ctl.h"
/*the value depending on dts config mem limit
*for skip two vframe case,need +2
*/
static unsigned int max_buf_num = VDIN_CANVAS_MAX_CNT;
static unsigned int min_buf_num = 4;
static unsigned int max_buf_width = VDIN_CANVAS_MAX_WIDTH_HD;
static unsigned int max_buf_height = VDIN_CANVAS_MAX_HEIGH;
/* one frame max metadata size:32x280 bits = 1120bytes(0x460) */
unsigned int dolby_size_byte = PAGE_SIZE;
#ifndef VDIN_DEBUG
#undef pr_info
#define pr_info(fmt, ...)
#endif
unsigned int max_buf_num = 4;
#ifdef DEBUG_SUPPORT
module_param(max_buf_num, uint, 0664);
MODULE_PARM_DESC(max_buf_num, "vdin max buf num.\n");
module_param(min_buf_num, uint, 0664);
MODULE_PARM_DESC(min_buf_num, "vdin min buf num.\n");
module_param(max_buf_width, uint, 0664);
MODULE_PARM_DESC(max_buf_width, "vdin max buf width.\n");
module_param(max_buf_height, uint, 0664);
MODULE_PARM_DESC(max_buf_height, "vdin max buf height.\n");
module_param(dolby_size_byte, uint, 0664);
MODULE_PARM_DESC(dolby_size_byte, "dolby_size_byte.\n");
#endif
const unsigned int vdin_canvas_ids[2][VDIN_CANVAS_MAX_CNT] = {
{
38, 39, 40, 41, 42,
@@ -47,6 +69,11 @@ const unsigned int vdin_canvas_ids[2][VDIN_CANVAS_MAX_CNT] = {
},
};
/*function:
* 1.set canvas_max_w & canvas_max_h
* 2.set canvas_max_size & canvas_max_num
* 3.set canvas_id & canvas_addr
*/
void vdin_canvas_init(struct vdin_dev_s *devp)
{
int i, canvas_id;
@@ -63,7 +90,7 @@ void vdin_canvas_init(struct vdin_dev_s *devp)
devp->canvas_max_num = VDIN_CANVAS_MAX_CNT;
devp->mem_start = roundup(devp->mem_start, 32);
pr_info("vdin.%d cnavas initial table:\n", devp->index);
pr_info("vdin.%d canvas initial table:\n", devp->index);
for (i = 0; i < devp->canvas_max_num; i++) {
canvas_id = vdin_canvas_ids[devp->index][i];
canvas_addr = devp->mem_start + devp->canvas_max_size * i;
@@ -79,84 +106,16 @@ void vdin_canvas_init(struct vdin_dev_s *devp)
}
}
void vdin_canvas_start_config(struct vdin_dev_s *devp)
{
int i, canvas_id;
unsigned long canvas_addr;
unsigned int canvas_max_w = 0;
unsigned int canvas_max_h = VDIN_CANVAS_MAX_HEIGH;
unsigned int canvas_num = VDIN_CANVAS_MAX_CNT;
unsigned int chroma_size = 0;
unsigned int canvas_step = 1;
canvas_max_w = VDIN_CANVAS_MAX_WIDTH_HD << 1;
if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB)) {
devp->canvas_w = devp->h_active * 3;
} else if ((devp->prop.dest_cfmt == TVIN_NV12) ||
(devp->prop.dest_cfmt == TVIN_NV21)) {
canvas_max_w = VDIN_CANVAS_MAX_WIDTH_HD;
canvas_max_h = VDIN_CANVAS_MAX_HEIGH;
canvas_num >>= 1;
canvas_step = 2;
devp->canvas_w = devp->h_active;
} else{
devp->canvas_w = devp->h_active * 2;
}
if (devp->source_bitdepth > 8)
devp->canvas_w = devp->canvas_w * 3 / 2;
#if 0
const struct tvin_format_s *fmt_info =
tvin_get_fmt_info(devp->parm.info.fmt);
if (fmt_info->scan_mode == TVIN_SCAN_MODE_INTERLACED)
devp->canvas_h = devp->v_active * 2;
else
devp->canvas_h = devp->v_active;
#else
devp->canvas_h = devp->v_active;
#endif
if ((devp->prop.dest_cfmt == TVIN_NV12) ||
(devp->prop.dest_cfmt == TVIN_NV21))
chroma_size = canvas_max_w*canvas_max_h/2;
devp->canvas_max_size =
PAGE_ALIGN((canvas_max_w*canvas_max_h+chroma_size));
devp->canvas_max_num = devp->mem_size / devp->canvas_max_size;
devp->canvas_max_num = min(devp->canvas_max_num, canvas_num);
devp->canvas_max_num = min(devp->canvas_max_num, max_buf_num);
devp->canvas_w = roundup(devp->canvas_w, 32);
devp->mem_start = roundup(devp->mem_start, 32);
pr_info("vdin.%d cnavas configuration table:\n", devp->index);
for (i = 0; i < devp->canvas_max_num; i++) {
canvas_id = vdin_canvas_ids[devp->index][i*canvas_step];
/* canvas_addr = canvas_get_addr(canvas_id); */
/*reinitlize the canvas*/
canvas_addr = devp->mem_start + devp->canvas_max_size * i;
canvas_config(canvas_id, canvas_addr, devp->canvas_w,
devp->canvas_h,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
if (chroma_size)
canvas_config(canvas_id+1,
canvas_addr+devp->canvas_w*devp->canvas_h,
devp->canvas_w, devp->canvas_h/2,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
pr_info("\t0x%2x: 0x%lx-0x%lx %ux%u\n",
canvas_id, canvas_addr,
canvas_addr + devp->canvas_max_size,
devp->canvas_w, devp->canvas_h);
}
}
/*
*this function used for configure canvas base on the input format
*also used for input resalution over 1080p such as camera input 200M,500M
*YUV422-8BIT:1pixel = 2byte;
*YUV422-10BIT:1pixel = 3byte;
*YUV444-8BIT:1pixel = 3byte;
*YUV444-10BIT:1pixel = 4bypte
/*function:canvas_config when canvas_config_mode=1
* 1.set canvas_w and canvas_h
* 2.set canvas_max_size and canvas_max_num
* 3.when dest_cfmt is TVIN_NV12/TVIN_NV21,
* buf width add canvas_w*canvas_h
*based on parameters:
* format_convert/ source_bitdepth/
* v_active color_depth_mode/ prop.dest_cfmt
*/
void vdin_canvas_auto_config(struct vdin_dev_s *devp)
void vdin_canvas_start_config(struct vdin_dev_s *devp)
{
int i = 0;
int canvas_id;
@@ -164,36 +123,47 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp)
unsigned int chroma_size = 0;
unsigned int canvas_step = 1;
unsigned int canvas_num = VDIN_CANVAS_MAX_CNT;
unsigned int max_buffer_num = max_buf_num;
/* todo: if new add output YUV444 format,this place should add too!!*/
if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB)) {
if (devp->source_bitdepth > 8)
devp->canvas_w = devp->h_active * 4;
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) ||
(devp->force_yuv444_malloc == 1)) {
if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)
devp->canvas_w = max_buf_width *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
else
devp->canvas_w = devp->h_active * 3;
} else if (((devp->prop.dest_cfmt == TVIN_NV12) ||
(devp->prop.dest_cfmt == TVIN_NV21)) &&
(devp->source_bitdepth <= 8)) {
devp->canvas_w = devp->h_active;
devp->canvas_w = max_buf_height *
VDIN_YUV444_8BIT_PER_PIXEL_BYTE;
} else if ((devp->prop.dest_cfmt == TVIN_NV12) ||
(devp->prop.dest_cfmt == TVIN_NV21)) {
devp->canvas_w = max_buf_width;
canvas_num = canvas_num/2;
canvas_step = 2;
} else{/*YUV422*/
/* txl new add yuv422 pack mode:canvas-w=h*2*10/8*/
if ((devp->source_bitdepth > 8) &&
/* txl new add yuv422 pack mode:canvas_w=h*2*10/8*/
if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) &&
(devp->color_depth_mode == 1))
devp->canvas_w = (devp->h_active * 5)/2;
else if ((devp->source_bitdepth > 8) &&
devp->canvas_w = (max_buf_width * 5)/2;
else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
(devp->color_depth_mode == 0))
devp->canvas_w = devp->h_active * 3;
devp->canvas_w = max_buf_width *
VDIN_YUV422_10BIT_PER_PIXEL_BYTE;
else
devp->canvas_w = devp->h_active * 2;
devp->canvas_w = max_buf_width *
VDIN_YUV422_8BIT_PER_PIXEL_BYTE;
}
/*backup before roundup*/
devp->canvas_active_w = devp->canvas_w;
/*canvas_w must ensure divided exact by 256bit(32byte)*/
devp->canvas_w = roundup(devp->canvas_w, 32);
devp->canvas_h = devp->v_active;
@@ -207,30 +177,448 @@ void vdin_canvas_auto_config(struct vdin_dev_s *devp)
devp->canvas_max_num = devp->mem_size / devp->canvas_max_size;
devp->canvas_max_num = min(devp->canvas_max_num, canvas_num);
devp->canvas_max_num = min(devp->canvas_max_num, max_buf_num);
devp->canvas_max_num = min(devp->canvas_max_num, max_buffer_num);
devp->mem_start = roundup(devp->mem_start, 32);
if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100)) {
/*use_reserved_mem or alloc_from_contiguous*/
devp->mem_start = roundup(devp->mem_start, 32);
#ifdef VDIN_DEBUG
pr_info("vdin%d cnavas auto configuration table:\n", devp->index);
pr_info("vdin%d cnavas start configuration table:\n",
devp->index);
#endif
for (i = 0; i < devp->canvas_max_num; i++) {
canvas_id = vdin_canvas_ids[devp->index][i*canvas_step];
canvas_addr = devp->mem_start + devp->canvas_max_size * i;
canvas_config(canvas_id, canvas_addr,
devp->canvas_w, devp->canvas_h,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
if (chroma_size)
canvas_config(canvas_id+1,
canvas_addr+devp->canvas_w*devp->canvas_h,
devp->canvas_w,
devp->canvas_h/2,
for (i = 0; i < devp->canvas_max_num; i++) {
canvas_id = vdin_canvas_ids[devp->index][i*canvas_step];
canvas_addr = devp->mem_start +
devp->canvas_max_size * i;
canvas_config(canvas_id, canvas_addr,
devp->canvas_w, devp->canvas_h,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
if (chroma_size)
canvas_config(canvas_id+1,
canvas_addr +
devp->canvas_w*devp->canvas_h,
devp->canvas_w,
devp->canvas_h/2,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#ifdef VDIN_DEBUG
pr_info("\t%3d: 0x%lx-0x%lx %ux%u\n",
canvas_id, canvas_addr,
canvas_addr + devp->canvas_max_size,
devp->canvas_w, devp->canvas_h);
pr_info("\t%3d: 0x%lx-0x%lx %ux%u\n",
canvas_id, canvas_addr,
canvas_addr + devp->canvas_max_size,
devp->canvas_w, devp->canvas_h);
#endif
}
} else if (devp->cma_config_flag & 0x100) {
#ifdef VDIN_DEBUG
pr_info("vdin%d cnavas start configuration table:\n",
devp->index);
#endif
for (i = 0; i < devp->canvas_max_num; i++) {
devp->vfmem_start[i] =
roundup(devp->vfmem_start[i], 32);
canvas_id = vdin_canvas_ids[devp->index][i*canvas_step];
canvas_addr = devp->vfmem_start[i];
canvas_config(canvas_id, canvas_addr,
devp->canvas_w, devp->canvas_h,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
if (chroma_size)
canvas_config(canvas_id+1,
canvas_addr +
devp->canvas_w*devp->canvas_h,
devp->canvas_w,
devp->canvas_h/2,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#ifdef VDIN_DEBUG
pr_info("\t%3d: 0x%lx-0x%lx %ux%u\n",
canvas_id, canvas_addr,
canvas_addr + devp->canvas_max_size,
devp->canvas_w, devp->canvas_h);
#endif
}
}
}
/*
*this function used for configure canvas when canvas_config_mode=2
*base on the input format
*also used for input resalution over 1080p such as camera input 200M,500M
*YUV422-8BIT:1pixel = 2byte;
*YUV422-10BIT:1pixel = 3byte;
*YUV422-10BIT-FULLPACK:1pixel = 2.5byte;
*YUV444-8BIT:1pixel = 3byte;
*YUV444-10BIT:1pixel = 4byte
*/
void vdin_canvas_auto_config(struct vdin_dev_s *devp)
{
int i = 0;
int canvas_id;
unsigned long canvas_addr;
unsigned int chroma_size = 0;
unsigned int canvas_step = 1;
unsigned int canvas_num = VDIN_CANVAS_MAX_CNT;
unsigned int max_buffer_num = max_buf_num;
/* todo: if new add output YUV444 format,this place should add too!!*/
if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) ||
(devp->force_yuv444_malloc == 1)) {
if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)
devp->canvas_w = devp->h_active *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
else
devp->canvas_w = devp->h_active *
VDIN_YUV444_8BIT_PER_PIXEL_BYTE;
} else if ((devp->prop.dest_cfmt == TVIN_NV12) ||
(devp->prop.dest_cfmt == TVIN_NV21)) {
canvas_num = canvas_num/2;
canvas_step = 2;
devp->canvas_w = devp->h_active;
/* nv21/nv12 only have 8bit mode */
} else {/*YUV422*/
/* txl new add yuv422 pack mode:canvas-w=h*2*10/8*/
if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) &&
(devp->color_depth_mode == 1))
devp->canvas_w = (devp->h_active * 5)/2;
else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
(devp->color_depth_mode == 0))
devp->canvas_w = devp->h_active *
VDIN_YUV422_10BIT_PER_PIXEL_BYTE;
else
devp->canvas_w = devp->h_active *
VDIN_YUV422_8BIT_PER_PIXEL_BYTE;
}
/*backup before roundup*/
devp->canvas_active_w = devp->canvas_w;
/*canvas_w must ensure divided exact by 256bit(32byte)*/
devp->canvas_w = roundup(devp->canvas_w, 32);
devp->canvas_h = devp->v_active;
if ((devp->prop.dest_cfmt == TVIN_NV12) ||
(devp->prop.dest_cfmt == TVIN_NV21))
chroma_size = devp->canvas_w*devp->canvas_h/2;
devp->canvas_max_size = PAGE_ALIGN(devp->canvas_w*
devp->canvas_h+chroma_size);
devp->canvas_max_num = devp->mem_size / devp->canvas_max_size;
devp->canvas_max_num = min(devp->canvas_max_num, canvas_num);
devp->canvas_max_num = min(devp->canvas_max_num, max_buffer_num);
if ((devp->cma_config_en != 1) || !(devp->cma_config_flag & 0x100)) {
/*use_reserved_mem or alloc_from_contiguous*/
devp->mem_start = roundup(devp->mem_start, 32);
#ifdef VDIN_DEBUG
pr_info("vdin%d cnavas auto configuration table:\n",
devp->index);
#endif
for (i = 0; i < devp->canvas_max_num; i++) {
canvas_id = vdin_canvas_ids[devp->index][i*canvas_step];
canvas_addr = devp->mem_start +
devp->canvas_max_size * i;
canvas_config(canvas_id, canvas_addr,
devp->canvas_w, devp->canvas_h,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
if (chroma_size)
canvas_config(canvas_id+1,
canvas_addr +
devp->canvas_w*devp->canvas_h,
devp->canvas_w,
devp->canvas_h/2,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#ifdef VDIN_DEBUG
pr_info("\t%3d: 0x%lx-0x%lx %ux%u\n",
canvas_id, canvas_addr,
canvas_addr + devp->canvas_max_size,
devp->canvas_w, devp->canvas_h);
#endif
}
} else if (devp->cma_config_flag & 0x100) {
#ifdef VDIN_DEBUG
pr_info("vdin%d cnavas auto configuration table:\n",
devp->index);
#endif
for (i = 0; i < devp->canvas_max_num; i++) {
devp->vfmem_start[i] =
roundup(devp->vfmem_start[i], 32);
canvas_id = vdin_canvas_ids[devp->index][i*canvas_step];
canvas_addr = devp->vfmem_start[i];
canvas_config(canvas_id, canvas_addr,
devp->canvas_w, devp->canvas_h,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
if (chroma_size)
canvas_config(canvas_id+1,
canvas_addr +
devp->canvas_w*devp->canvas_h,
devp->canvas_w,
devp->canvas_h/2,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#ifdef VDIN_DEBUG
pr_info("\t%3d: 0x%lx-0x%lx %ux%u\n",
canvas_id, canvas_addr,
canvas_addr + devp->canvas_max_size,
devp->canvas_w, devp->canvas_h);
#endif
}
}
}
#ifdef CONFIG_CMA
/* return val:1: fail;0: ok */
unsigned int vdin_cma_alloc(struct vdin_dev_s *devp)
{
char vdin_name[6];
unsigned int mem_size, h_size, v_size;
int flags = CODEC_MM_FLAGS_CMA_FIRST|CODEC_MM_FLAGS_CMA_CLEAR|
CODEC_MM_FLAGS_CPU;
unsigned int max_buffer_num = min_buf_num;
unsigned int i;
if (devp->rdma_enable && (devp->game_mode == 0))
max_buffer_num++;
/*todo: need update if vf_skip_cnt used by other port*/
if (devp->vfp->skip_vf_num &&
(((devp->parm.port >= TVIN_PORT_HDMI0) &&
(devp->parm.port <= TVIN_PORT_HDMI7)) ||
((devp->parm.port >= TVIN_PORT_CVBS0) &&
(devp->parm.port <= TVIN_PORT_CVBS7))))
max_buffer_num += devp->vfp->skip_vf_num;
if (max_buffer_num > max_buf_num)
max_buffer_num = max_buf_num;
devp->vfmem_max_cnt = max_buffer_num;
if ((devp->cma_config_en == 0) ||
(devp->cma_mem_alloc == 1)) {
pr_info("\nvdin%d %s use_reserved mem or cma already alloced (%d,%d)!!!\n",
devp->index, __func__, devp->cma_config_en,
devp->cma_mem_alloc);
return 0;
}
h_size = devp->h_active;
v_size = devp->v_active;
if (devp->canvas_config_mode == 1) {
h_size = max_buf_width;
v_size = max_buf_height;
}
if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) ||
(devp->force_yuv444_malloc == 1)) {
if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) {
h_size = roundup(h_size *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE, 32);
devp->canvas_alin_w = h_size /
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
} else {
h_size = roundup(h_size *
VDIN_YUV444_8BIT_PER_PIXEL_BYTE, 32);
devp->canvas_alin_w = h_size /
VDIN_YUV444_8BIT_PER_PIXEL_BYTE;
}
} else if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_NV12) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_NV21) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_NV12) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_NV21)) {
h_size = roundup(h_size, 32);
devp->canvas_alin_w = h_size;
/*todo change with canvas alloc!!*/
/* nv21/nv12 only have 8bit mode */
} else {
/* txl new add mode yuv422 pack mode:canvas-w=h*2*10/8
*canvas_w must ensure divided exact by 256bit(32byte
*/
if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) &&
(devp->color_depth_mode == 1)) {
h_size = roundup((h_size * 5)/2, 32);
devp->canvas_alin_w = (h_size * 2) / 5;
} else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
(devp->color_depth_mode == 0)) {
h_size = roundup(h_size *
VDIN_YUV422_10BIT_PER_PIXEL_BYTE, 32);
devp->canvas_alin_w = h_size /
VDIN_YUV422_10BIT_PER_PIXEL_BYTE;
} else {
h_size = roundup(h_size *
VDIN_YUV422_8BIT_PER_PIXEL_BYTE, 32);
devp->canvas_alin_w = h_size /
VDIN_YUV422_8BIT_PER_PIXEL_BYTE;
}
}
mem_size = h_size * v_size;
if ((devp->format_convert >= VDIN_FORMAT_CONVERT_YUV_NV12) &&
(devp->format_convert <= VDIN_FORMAT_CONVERT_RGB_NV21))
mem_size = (mem_size * 3)/2;
devp->vfmem_size = PAGE_ALIGN(mem_size) + dolby_size_byte;
devp->vfmem_size = (devp->vfmem_size/PAGE_SIZE + 1)*PAGE_SIZE;
mem_size = PAGE_ALIGN(mem_size) * max_buffer_num +
dolby_size_byte * max_buffer_num;
mem_size = (mem_size/PAGE_SIZE + 1)*PAGE_SIZE;
if (mem_size > devp->cma_mem_size)
mem_size = devp->cma_mem_size;
if (devp->index == 0)
strcpy(vdin_name, "vdin0");
else if (devp->index == 1)
strcpy(vdin_name, "vdin1");
if (devp->cma_config_flag == 0x101) {
for (i = 0; i < max_buffer_num; i++) {
devp->vfmem_start[i] = codec_mm_alloc_for_dma(vdin_name,
devp->vfmem_size/PAGE_SIZE, 0, flags);
if (devp->vfmem_start[i] == 0) {
pr_err("\nvdin%d buf[%d]codec alloc fail!!!\n",
devp->index, i);
devp->cma_mem_alloc = 0;
return 1;
}
devp->cma_mem_alloc = 1;
pr_info("vdin%d buf[%d] mem_start = 0x%lx, mem_size = 0x%x\n",
devp->index, i,
devp->vfmem_start[i], devp->vfmem_size);
}
pr_info("vdin%d codec cma alloc ok!\n", devp->index);
devp->mem_size = mem_size;
} else if (devp->cma_config_flag == 0x1) {
devp->mem_start = codec_mm_alloc_for_dma(vdin_name,
mem_size/PAGE_SIZE, 0, flags);
devp->mem_size = mem_size;
if (devp->mem_start == 0) {
pr_err("\nvdin%d codec alloc fail!!!\n",
devp->index);
devp->cma_mem_alloc = 0;
return 1;
}
devp->cma_mem_alloc = 1;
pr_info("vdin%d mem_start = 0x%lx, mem_size = 0x%x\n",
devp->index, devp->mem_start, devp->mem_size);
pr_info("vdin%d codec cma alloc ok!\n", devp->index);
} else if (devp->cma_config_flag == 0x100) {
for (i = 0; i < max_buffer_num; i++) {
devp->vfvenc_pages[i] = dma_alloc_from_contiguous(
&(devp->this_pdev->dev),
devp->vfmem_size >> PAGE_SHIFT, 0);
if (devp->vfvenc_pages[i]) {
devp->vfmem_start[i] =
page_to_phys(devp->vfvenc_pages[i]);
pr_info("vdin%d buf[%d]mem_start = 0x%lx, mem_size = 0x%x\n",
devp->index, i,
devp->vfmem_start[i], devp->vfmem_size);
} else {
devp->cma_mem_alloc = 0;
pr_err("\nvdin%d cma mem undefined2.\n",
devp->index);
return 1;
}
}
devp->cma_mem_alloc = 1;
devp->mem_size = mem_size;
pr_info("vdin%d cma alloc ok!\n", devp->index);
} else {
devp->venc_pages = dma_alloc_from_contiguous(
&(devp->this_pdev->dev),
devp->cma_mem_size >> PAGE_SHIFT, 0);
if (devp->venc_pages) {
devp->mem_start =
page_to_phys(devp->venc_pages);
devp->mem_size = mem_size;
devp->cma_mem_alloc = 1;
pr_info("vdin%d mem_start = 0x%lx, mem_size = 0x%x\n",
devp->index, devp->mem_start, devp->mem_size);
pr_info("vdin%d cma alloc ok!\n", devp->index);
} else {
devp->cma_mem_alloc = 0;
pr_err("\nvdin%d cma mem undefined2.\n",
devp->index);
return 1;
}
}
return 0;
}
/*this function used for codec cma release
* 1.call codec_mm_free_for_dma() or
* dma_release_from_contiguous() to relase cma;
* 2.reset mem_start & mem_size & cma_mem_alloc to 0;
*/
void vdin_cma_release(struct vdin_dev_s *devp)
{
char vdin_name[6];
unsigned int i;
if ((devp->cma_config_en == 0) ||
(devp->cma_mem_alloc == 0)) {
pr_err("\nvdin%d %s fail for (%d,%d)!!!\n",
devp->index, __func__, devp->cma_config_en,
devp->cma_mem_alloc);
return;
}
if (devp->index == 0)
strcpy(vdin_name, "vdin0");
else if (devp->index == 1)
strcpy(vdin_name, "vdin1");
if (devp->cma_config_flag == 0x101) {
for (i = 0; i < devp->vfmem_max_cnt; i++)
codec_mm_free_for_dma(vdin_name, devp->vfmem_start[i]);
pr_info("vdin%d codec cma release ok!\n", devp->index);
} else if (devp->cma_config_flag == 0x1) {
codec_mm_free_for_dma(vdin_name, devp->mem_start);
pr_info("vdin%d codec cma release ok!\n", devp->index);
} else if (devp->cma_config_flag == 0x100) {
for (i = 0; i < devp->vfmem_max_cnt; i++)
dma_release_from_contiguous(
&(devp->this_pdev->dev),
devp->vfvenc_pages[i],
devp->vfmem_size >> PAGE_SHIFT);
pr_info("vdin%d cma release ok!\n", devp->index);
} else if (devp->venc_pages
&& devp->cma_mem_size
&& (devp->cma_config_flag == 0)) {
dma_release_from_contiguous(
&(devp->this_pdev->dev),
devp->venc_pages,
devp->cma_mem_size >> PAGE_SHIFT);
pr_info("vdin%d cma release ok!\n", devp->index);
} else {
pr_err("\nvdin%d %s fail for (%d,0x%x,0x%lx)!!!\n",
devp->index, __func__, devp->cma_mem_size,
devp->cma_config_flag, devp->mem_start);
}
devp->mem_start = 0;
devp->mem_size = 0;
devp->cma_mem_alloc = 0;
}
/*@20170823 new add for the case of csc change after signal stable*/
void vdin_cma_malloc_mode(struct vdin_dev_s *devp)
{
unsigned int h_size, v_size;
h_size = devp->h_active;
v_size = devp->v_active;
if ((h_size <= VDIN_YUV444_MAX_CMA_WIDTH) &&
(v_size <= VDIN_YUV444_MAX_CMA_HEIGH) &&
(devp->cma_mem_mode == 1))
devp->force_yuv444_malloc = 1;
else
devp->force_yuv444_malloc = 0;
}
#endif

17
drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.h
View File

@@ -19,22 +19,27 @@
#define __VDIN_CANVAS_H
#include <linux/sizes.h>
#include <linux/amlogic/media/canvas/canvas.h>
#include <linux/amlogic/media/vfm/vframe.h>
#define VDIN_CANVAS_MAX_WIDTH_UHD 4096
#define VDIN_CANVAS_MAX_WIDTH_HD 1920
#define VDIN_CANVAS_MAX_HEIGH 2228
#define VDIN_YUV422_8BIT_PER_PIXEL_BYTE 2
#define VDIN_YUV422_10BIT_PER_PIXEL_BYTE 3
#define VDIN_YUV444_10BIT_PER_PIXEL_BYTE 4
#define VDIN_YUV444_8BIT_PER_PIXEL_BYTE 3
#define VDIN_MIN_SOURCE_BITDEPTH 8
#define VDIN_CANVAS_MAX_CNT 9
#define VDIN_YUV444_MAX_CMA_WIDTH 1920
#define VDIN_YUV444_MAX_CMA_HEIGH 1080
extern const unsigned int vdin_canvas_ids[2][VDIN_CANVAS_MAX_CNT];
extern void vdin_canvas_init(struct vdin_dev_s *devp);
extern void vdin_canvas_start_config(struct vdin_dev_s *devp);
extern void vdin_canvas_auto_config(struct vdin_dev_s *devp);
extern unsigned int vdin_cma_alloc(struct vdin_dev_s *devp);
extern void vdin_cma_release(struct vdin_dev_s *devp);
extern void vdin_cma_malloc_mode(struct vdin_dev_s *devp);
#endif /* __VDIN_CANVAS_H */

1897
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
View File

File diff suppressed because it is too large Load Diff

67
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h
View File

@@ -18,12 +18,15 @@
#ifndef __TVIN_VDIN_CTL_H
#define __TVIN_VDIN_CTL_H
#include <linux/amlogic/media/vfm/vframe.h>
#include "vdin_drv.h"
#define DV_SWAP_EN (1 << 0)
#define DV_BUF_START_RESET (1 << 1)
#define DV_FRAME_BUF_START_RESET (1 << 2)
#define DV_UPDATE_DATA_MODE_DELBY_WORK (1 << 4)
#define DV_CLEAN_UP_MEM (1 << 5)
#define DV_READ_MODE_AXI (1 << 6)
#define DV_CRC_CHECK (1 << 7)
/* *********************************************************************** */
/* *** enum definitions ********************************************* */
@@ -92,12 +95,7 @@ struct vdin_matrix_lup_s {
unsigned int post_offset2;
};
struct vdin_stat_s {
unsigned int sum_luma; /* VDIN_HIST_LUMA_SUM_REG */
unsigned int sum_pixel; /* VDIN_HIST_PIX_CNT_REG */
};
#ifdef CONFIG_AMLOGIC_LOCAL_DIMMING
#ifdef CONFIG_AML_LOCAL_DIMMING
struct ldim_max_s {
/* general parameters */
int ld_pic_rowmax;
@@ -107,15 +105,6 @@ struct ldim_max_s {
};
#endif
struct vdin_hist_cfg_s {
unsigned int pow;
unsigned int win_en;
unsigned int rd_en;
unsigned int hstart;
unsigned int hend;
unsigned int vstart;
unsigned int vend;
};
/* ************************************************************************ */
/* ******** GLOBAL FUNCTION CLAIM ******** */
@@ -156,18 +145,13 @@ extern void vdin_set_chma_canvas_id(struct vdin_dev_s *devp,
unsigned int rdma_enable, unsigned int canvas_id);
extern void vdin_enable_module(unsigned int offset, bool enable);
extern void vdin_set_matrix(struct vdin_dev_s *devp);
void vdin_set_matrixs(struct vdin_dev_s *devp, unsigned char no,
extern void vdin_set_matrixs(struct vdin_dev_s *devp, unsigned char no,
enum vdin_format_convert_e csc);
extern void vdin_set_matrix_blank(struct vdin_dev_s *devp);
extern void vdin_delay_line(unsigned short num, unsigned int offset);
extern void set_wr_ctrl(int h_pos, int v_pos, struct vdin_dev_s *devp);
extern bool vdin_check_cycle(struct vdin_dev_s *devp);
extern bool vdin_write_done_check(unsigned int offset,
struct vdin_dev_s *devp);
extern bool vdin_check_vs(struct vdin_dev_s *devp);
extern void vdin_calculate_duration(struct vdin_dev_s *devp);
extern void vdin_output_ctl(unsigned int offset,
unsigned int output_flag);
extern void vdin_wr_reverse(unsigned int offset, bool hreverse,
bool vreverse);
extern void vdin_set_hvscale(struct vdin_dev_s *devp);
@@ -178,6 +162,39 @@ extern void vdin_bypass_isp(unsigned int offset);
extern void vdin_set_mpegin(struct vdin_dev_s *devp);
extern void vdin_force_gofiled(struct vdin_dev_s *devp);
extern void vdin_set_config(struct vdin_dev_s *devp);
extern void vdin_set_wr_mif(struct vdin_dev_s *devp);
extern void vdin_dolby_config(struct vdin_dev_s *devp);
extern void vdin_dolby_buffer_update(struct vdin_dev_s *devp,
unsigned int index);
extern void vdin_dolby_addr_update(struct vdin_dev_s *devp, unsigned int index);
extern void vdin_dolby_addr_alloc(struct vdin_dev_s *devp, unsigned int size);
extern void vdin_dolby_addr_release(struct vdin_dev_s *devp, unsigned int size);
extern int vdin_event_cb(int type, void *data, void *op_arg);
extern void vdin_hdmiin_patch(struct vdin_dev_s *devp);
extern void vdin_set_top(unsigned int offset,
enum tvin_port_e port,
enum tvin_color_fmt_e input_cfmt, unsigned int h,
enum bt_path_e bt_path);
extern void vdin_set_wr_ctrl_vsync(struct vdin_dev_s *devp,
unsigned int offset, enum vdin_format_convert_e format_convert,
unsigned int color_depth_mode, unsigned int source_bitdeth,
unsigned int rdma_enable);
extern void vdin_urgent_patch_resume(unsigned int offset);
extern void vdin_set_drm_data(struct vdin_dev_s *devp,
struct vframe_s *vf);
extern u32 vdin_get_curr_field_type(struct vdin_dev_s *devp);
extern void vdin_set_source_type(struct vdin_dev_s *devp,
struct vframe_s *vf);
extern void vdin_set_source_mode(struct vdin_dev_s *devp,
struct vframe_s *vf);
extern void vdin_set_source_bitdepth(struct vdin_dev_s *devp,
struct vframe_s *vf);
extern void vdin_set_pixel_aspect_ratio(struct vdin_dev_s *devp,
struct vframe_s *vf);
extern void vdin_set_display_ratio(struct vdin_dev_s *devp,
struct vframe_s *vf);
extern void vdin_source_bitdepth_reinit(struct vdin_dev_s *devp);
extern void set_invert_top_bot(bool invert_flag);
#endif

1272
drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c
View File

File diff suppressed because it is too large Load Diff

1641
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

File diff suppressed because it is too large Load Diff

293
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h
View File

@@ -20,7 +20,6 @@
/* Standard Linux Headers */
#include <linux/cdev.h>
#include <linux/spinlock.h>
#include <linux/irqreturn.h>
#include <linux/timer.h>
#include <linux/mutex.h>
@@ -28,9 +27,6 @@
#include <linux/time.h>
#include <linux/device.h>
#include <linux/clk.h>
#if 0 /*todo: instead switch in linux 4.4?*/
#include <linux/switch.h>
#endif
#include <linux/workqueue.h>
/* Amlogic Headers */
@@ -45,12 +41,11 @@
#endif
/* Local Headers */
#include "../tvin_global.h"
#include "../tvin_frontend.h"
#include "vdin_vf.h"
#include "vdin_regs.h"
#define VDIN_VER "Ref.2016/10/14"
#define VDIN_VER "Ref.2017/011/17"
/*the counter of vdin*/
#define VDIN_MAX_DEVS 2
@@ -78,12 +73,18 @@
#define VDIN_FLAG_SNOW_FLAG 0x00004000
/*flag for disable vdin sm*/
#define VDIN_FLAG_SM_DISABLE 0x00008000
/*flag for vdin suspend state*/
#define VDIN_FLAG_SUSPEND 0x00010000
/*flag for vdin-v4l2 debug*/
#define VDIN_FLAG_V4L2_DEBUG 0x00020000
/*flag for isr req&free*/
#define VDIN_FLAG_ISR_REQ 0x00040000
/*values of vdin isr bypass check flag */
#define VDIN_BYPASS_STOP_CHECK 0x00000001
#define VDIN_BYPASS_CYC_CHECK 0x00000002
#define VDIN_BYPASS_VSYNC_CHECK 0x00000004
#define VDIN_BYPASS_VGA_CHECK 0x00000008
#define VDIN_CANVAS_MAX_CNT 9
/*flag for flush vdin buff*/
#define VDIN_FLAG_BLACK_SCREEN_ON 1
@@ -100,191 +101,216 @@
/*TXL new add*/
#define VDIN_WR_COLOR_DEPTH_10BIT_FULL_PCAK_MODE (1 << 4)
static inline const char *vdin_fmt_convert_str(
enum vdin_format_convert_e fmt_cvt)
{
switch (fmt_cvt) {
case VDIN_FORMAT_CONVERT_YUV_YUV422:
return "FMT_CONVERT_YUV_YUV422";
break;
case VDIN_FORMAT_CONVERT_YUV_YUV444:
return "FMT_CONVERT_YUV_YUV444";
break;
case VDIN_FORMAT_CONVERT_YUV_RGB:
return "FMT_CONVERT_YUV_RGB";
break;
case VDIN_FORMAT_CONVERT_RGB_YUV422:
return "FMT_CONVERT_RGB_YUV422";
break;
case VDIN_FORMAT_CONVERT_RGB_YUV444:
return "FMT_CONVERT_RGB_YUV444";
break;
case VDIN_FORMAT_CONVERT_RGB_RGB:
return "FMT_CONVERT_RGB_RGB";
break;
case VDIN_FORMAT_CONVERT_YUV_NV12:
return "VDIN_FORMAT_CONVERT_YUV_NV12";
break;
case VDIN_FORMAT_CONVERT_YUV_NV21:
return "VDIN_FORMAT_CONVERT_YUV_NV21";
break;
case VDIN_FORMAT_CONVERT_RGB_NV12:
return "VDIN_FORMAT_CONVERT_RGB_NV12";
break;
case VDIN_FORMAT_CONVERT_RGB_NV21:
return "VDIN_FORMAT_CONVERT_RGB_NV21";
break;
default:
return "FMT_CONVERT_NULL";
break;
}
}
/*******for debug **********/
struct vdin_debug_s {
struct tvin_cutwin_s cutwin;
unsigned short scaler4h;/* for vscaler */
unsigned short scaler4w;/* for hscaler */
unsigned short dest_cfmt;/* for color fmt conversion */
struct tvin_cutwin_s cutwin;
unsigned short scaler4h;/* for vscaler */
unsigned short scaler4w;/* for hscaler */
unsigned short dest_cfmt;/* for color fmt conversion */
};
struct vdin_dv_s {
struct vframe_provider_s vprov_dv;
struct delayed_work dv_dwork;
unsigned int dv_cur_index;
unsigned int dv_next_index;
unsigned int dolby_input;
dma_addr_t dv_dma_paddr;
void *dv_dma_vaddr;
unsigned int dv_flag_cnt;/*cnt for no dv input*/
bool dv_flag;
bool dv_config;
bool dv_crc_check;/*0:fail;1:ok*/
};
struct vdin_dev_s {
unsigned int index;
unsigned int vdin_max_pixelclk;
dev_t devt;
struct cdev cdev;
struct device *dev;
struct cdev cdev;
struct device *dev;
struct tvin_parm_s parm;
struct tvin_format_s *fmt_info_p;
struct vf_pool *vfp;
struct tvin_frontend_s *frontend;
struct tvin_sig_property_s pre_prop;
struct tvin_sig_property_s prop;
struct vframe_provider_s vprov;
struct vdin_dv_s dv;
char name[15];
/* bit0 TVIN_PARM_FLAG_CAP bit31: TVIN_PARM_FLAG_WORK_ON */
unsigned int flags;
unsigned int mem_start;
unsigned int mem_size;
/* start address of captured frame data [8 bits] in memory */
/* for Component input, frame data [8 bits] order is
* Y0Cb0Y1Cr0<EFBFBD><EFBFBD>Y2nCb2nY2n+1Cr2n<EFBFBD><EFBFBD>
*/
/* for VGA input, frame data [8 bits] order is
* R0G0B0<EFBFBD><EFBFBD>RnGnBn<EFBFBD><EFBFBD>
*/
unsigned int cap_addr;
unsigned int cap_size;
unsigned int h_active;
unsigned int v_active;
enum vdin_format_convert_e format_convert;
enum vframe_source_type_e source_type;
enum vframe_source_mode_e source_mode;
unsigned int source_bitdepth;
unsigned int *canvas_ids;
unsigned int canvas_h;
unsigned int canvas_w;
unsigned int canvas_max_size;
unsigned int canvas_max_num;
struct vf_entry *curr_wr_vfe;
struct vf_entry *last_wr_vfe;
unsigned int curr_field_type;
unsigned int irq;
unsigned int rdma_irq;
char irq_name[12];
/* address offset(vdin0/vdin1/...) */
unsigned int addr_offset;
unsigned int vga_clr_cnt;
unsigned int vs_cnt_valid;
unsigned int vs_cnt_ignore;
struct tvin_parm_s parm;
struct tvin_format_s *fmt_info_p;
struct vf_pool *vfp;
struct tvin_frontend_s *frontend;
struct tvin_sig_property_s pre_prop;
struct tvin_sig_property_s prop;
struct vframe_provider_s vprov;
/* 0:from gpio A,1:from csi2 , 2:gpio B*/
enum bt_path_e bt_path;
enum bt_path_e bt_path;
struct timer_list timer;
spinlock_t isr_lock;
struct mutex fe_lock;
struct clk *msr_clk;
unsigned int msr_clk_val;
struct vdin_debug_s debug;
enum vdin_format_convert_e format_convert;
unsigned int source_bitdepth;
struct timer_list timer;
spinlock_t dec_lock;
struct tasklet_struct isr_tasklet;
spinlock_t isr_lock;
struct mutex mm_lock; /* lock for mmap */
struct mutex fe_lock;
struct vf_entry *curr_wr_vfe;
struct vf_entry *last_wr_vfe;
unsigned int curr_field_type;
unsigned int unstable_flag;
unsigned int dec_enable;
unsigned int abnormal_cnt;
/* bool stamp_valid; use vfe replace tell the first frame */
unsigned int stamp;
unsigned int hcnt64;
unsigned int cycle;
unsigned int hcnt64_tag;
unsigned int cycle_tag;
unsigned int start_time;/* ms vdin start time */
bool send2di;
int rdma_handle;
struct clk *msr_clk;
unsigned int msr_clk_val;
char name[15];
/* bit0 TVIN_PARM_FLAG_CAP bit31: TVIN_PARM_FLAG_WORK_ON */
unsigned int flags;
unsigned int index;
unsigned int vdin_max_pixelclk;
/* signal event */
struct delayed_work sig_dwork;
struct workqueue_struct *sig_wq;
#if 0
struct switch_dev sig_sdev;
#endif
struct tvin_info_s pre_info;
unsigned long mem_start;
unsigned int mem_size;
unsigned long vfmem_start[VDIN_CANVAS_MAX_CNT];
struct page *vfvenc_pages[VDIN_CANVAS_MAX_CNT];
unsigned int vfmem_size;
unsigned int vfmem_max_cnt;
struct vdin_debug_s debug;
unsigned int cma_config_en;
/*cma_config_flag:1:share with codec_mm;0:cma alone*/
unsigned int cma_config_flag;
unsigned int h_active;
unsigned int v_active;
unsigned int canvas_h;
unsigned int canvas_w;
unsigned int canvas_active_w;
unsigned int canvas_alin_w;
unsigned int canvas_max_size;
unsigned int canvas_max_num;
unsigned int irq;
unsigned int rdma_irq;
char irq_name[12];
/* address offset(vdin0/vdin1/...) */
unsigned int addr_offset;
unsigned int vs_cnt_valid;
unsigned int vs_cnt_ignore;
unsigned int unstable_flag;
unsigned int abnormal_cnt;
unsigned int stamp;
unsigned int hcnt64;
unsigned int cycle;
unsigned int hcnt64_tag;
unsigned int cycle_tag;
unsigned int start_time;/* ms vdin start time */
int rdma_handle;
bool cma_config_en;
/*cma_config_flag:
*bit0: (1:share with codec_mm;0:cma alone)
*bit8: (1:discontinuous alloc way;0:continuous alloc way)
*/
unsigned int cma_config_flag;
#ifdef CONFIG_CMA
struct platform_device *this_pdev;
struct page *venc_pages;
unsigned int cma_mem_size;/*BYTE*/
unsigned int cma_mem_alloc;
struct page *venc_pages;
unsigned int cma_mem_size;/*BYTE*/
unsigned int cma_mem_alloc;
/*cma_mem_mode:0:according to input size and output fmt;
**1:according to input size and output fmt force as YUV444
*/
unsigned int cma_mem_mode;
unsigned int force_yuv444_malloc;
#endif
/* bit0: enable/disable; bit4: luma range info */
unsigned int csc_cfg;
bool csc_cfg;
/* duration of current timing */
unsigned int duration;
unsigned int duration;
/* color-depth for vdin write */
/* vdin write mem color depth support:
* bit0:support 8bit
* bit1:support 9bit
* bit2:support 10bit
* bit3:support 12bit
* bit4:support yuv422 10bit full pack mode (from txl new add)
/*vdin write mem color depth support:
*bit0:support 8bit
*bit1:support 9bit
*bit2:support 10bit
*bit3:support 12bit
*bit4:support yuv422 10bit full pack mode (from txl new add)
*/
unsigned int color_depth_support;
/* color depth config
* 0:auto config as frontend
* 8:force config as 8bit
* 10:force config as 10bit
* 12:force config as 12bit
unsigned int color_depth_support;
/*color depth config
*0:auto config as frontend
*8:force config as 8bit
*10:force config as 10bit
*12:force config as 12bit
*/
unsigned int color_depth_config;
unsigned int color_depth_config;
/* new add from txl:color depth mode for 10bit
* 1: full pack mode;config 10bit as 10bit
* 0: config 10bit as 12bit
*1: full pack mode;config 10bit as 10bit
*0: config 10bit as 12bit
*/
unsigned int color_depth_mode;
unsigned int color_depth_mode;
/* cutwindow config */
bool cutwindow_cfg;
bool auto_cutwindow_en;
/*
*1:vdin out limit range
*0:vdin out full range
*/
unsigned int color_range_mode;
/*auto detect av/atv input ratio*/
unsigned int auto_ratio_en;
bool game_mode;/*1:game mode for hdmi*/
unsigned int rdma_enable;
unsigned int canvas_config_mode;
bool prehsc_en;
bool vshrk_en;
bool urgent_en;
bool black_bar_enable;
bool hist_bar_enable;
/*use frame rate to cal duraton*/
unsigned int use_frame_rate;
unsigned int irq_cnt;
unsigned int rdma_irq_cnt;
unsigned int vdin_irq_flag;
unsigned int vdin_reset_flag;
unsigned int vdin_dev_ssize;
wait_queue_head_t queue;
};
#ifdef CONFIG_TVIN_VDIN_CTRL
int vdin_ctrl_open_fe(int no, int port);
int vdin_ctrl_close_fe(int no);
int vdin_ctrl_start_fe(int no, struct vdin_parm_s *para);
int vdin_ctrl_stop_fe(int no);
enum tvin_sig_fmt_e vdin_ctrl_get_fmt(int no);
#endif
extern bool enable_reset;
extern unsigned int max_buf_num;
extern unsigned int vdin_ldim_max_global[100];
extern struct vframe_provider_s *vf_get_provider_by_name(
const char *provider_name);
extern bool enable_reset;
extern unsigned int dolby_size_byte;
extern unsigned int dv_dbg_mask;
extern char *vf_get_receiver_name(const char *provider_name);
extern int start_tvin_service(int no, struct vdin_parm_s *para);
extern int stop_tvin_service(int no);
extern int vdin_reg_v4l2(struct vdin_v4l2_ops_s *v4l2_ops);
extern void vdin_unreg_v4l2(void);
extern int vdin_create_class_files(struct class *vdin_clsp);
extern void vdin_remove_class_files(struct class *vdin_clsp);
extern int vdin_create_device_files(struct device *dev);
@@ -307,5 +333,6 @@ extern void vdin_vf_reg(struct vdin_dev_s *devp);
extern void vdin_vf_unreg(struct vdin_dev_s *devp);
extern void vdin_pause_dec(struct vdin_dev_s *devp);
extern void vdin_resume_dec(struct vdin_dev_s *devp);
extern bool is_dolby_vision_enable(void);
#endif /* __TVIN_VDIN_DRV_H */

137
drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h
View File

@@ -18,11 +18,12 @@
#ifndef __VDIN_REGS_H
#define __VDIN_REGS_H
/* mmc */
#define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743
#define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744
#define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745
#define VPU_ARB_URG_CTRL 0x2747
#define VPU_WRARB_MODE_L2C1 0x27a2
#define VPU_ARB_DBG_STAT_L1C2 0x27b6
#define VDIN_DET_IDLE_BIT 8
#define VDIN_DET_IDLE_WIDTH 4
@@ -60,6 +61,8 @@
/* vpp */
#define VPP_VDO_MEAS_CTRL 0x1da8
#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d
/* VDIN0 8'h00 - 8'h7f */
/* VDIN1 8'h80 - 8'hef */
@@ -180,7 +183,7 @@
* is not sync with external signal
*/
/* Bit 24, decimation de enable */
/* Bit 23:20, decimation phase
/* Bit 23:20, decimation phase,
* which counter value use to decimate,
*/
/* Bit 19:16, decimation number, 0: not decimation,
@@ -333,7 +336,6 @@
#define VDIN_MATRIX_PROBE_POS ((0x122a))/* + 0xd0100000) */
#define VDIN_CHROMA_ADDR_PORT ((0x122b))/* + 0xd0100000) */
#define VDIN_CHROMA_DATA_PORT ((0x122c))/* + 0xd0100000) */
/* */
#define VDIN_CM_BRI_CON_CTRL ((0x122d))/* + 0xd0100000) */
/* Bit 17 clk_cyc_cnt_clr, if true, clear this register */
/* Bit 16 if true, use vpu clock to count one line,
@@ -544,7 +546,7 @@
/* Bit 31:29 Reserved */
/* Bit 28:16 blkbar_row_th1. //threshold of the top blackbar */
/* Bit 15:13 Reserved */
/* bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar */
/* bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar*/
#define VDIN_BLKBAR_ROW_TH1_TH2 ((0x1264))/* + 0xd0100000) */
/* Readonly */
/* Bit 31:29 Reserved */
@@ -608,8 +610,8 @@
/* Bit 28:16 input window H start */
/* Bit 12:0 input window H end */
#define VDIN_WIN_H_START_END ((0x126d))/* + 0xd0100000) */
/* Bit 28:16 input window H start */
/* Bit 12:0 input window V start */
/* Bit 28:16 input window V start */
/* Bit 12:0 input window V end */
#define VDIN_WIN_V_START_END ((0x126e))/* + 0xd0100000) */
/* Bit 23:16 vdi8 asfifo_ctrl */
/* Bit 15:8 vdi7 asfifo_ctrl */
@@ -629,6 +631,20 @@
/* Bit 5:0, vdi9_asfifo_cnt */
#define VDIN_COM_STATUS3 ((0x1273))/* + 0xd0100000) */
/* dolby vdin regs */
#define VDIN_DOLBY_DSC_CTRL0 0x1275
/*((0x1275 << 2) + 0xff900000)*/
#define VDIN_DOLBY_DSC_CTRL1 0x1276
#define VDIN_DOLBY_DSC_CTRL2 0x1277
#define VDIN_DOLBY_DSC_CTRL3 0x1278
#define VDIN_DOLBY_AXI_CTRL0 0x1279
#define VDIN_DOLBY_AXI_CTRL1 0x127a
#define VDIN_DOLBY_AXI_CTRL2 0x127b
#define VDIN_DOLBY_AXI_CTRL3 0x127c
#define VDIN_DOLBY_DSC_STATUS0 0x127d
#define VDIN_DOLBY_DSC_STATUS1 0x127e
#define VDIN_DOLBY_DSC_STATUS2 0x127f
#define VDIN_DOLBY_DSC_STATUS3 0x121d
@@ -637,13 +653,13 @@
/* #define VDIN_COM_CTRL0 0x1202 */
/* used by other modules,indicates that MPEG input.
* 0: mpeg source to NR directly,
* 1: mpeg source pass through here
*0: mpeg source to NR directly,
*1: mpeg source pass through here
*/
#define MPEG_TO_VDIN_SEL_BIT 31
#define MPEG_TO_VDIN_SEL_WID 1
/* indicates MPEG field ID,written by software.
* 0: EVEN FIELD 1: ODD FIELD
*0: EVEN FIELD 1: ODD FIELD
*/
#define MPEG_FLD_BIT 30
#define MPEG_FLD_WID 1
@@ -667,21 +683,16 @@
/* 00: component0_in 01: component1_in 10: component2_in */
#define COMP0_OUT_SWT_BIT 6
#define COMP0_OUT_SWT_WID 2
#define INPUT_WIN_SEL_EN_BIT 5
#define INPUT_WIN_SEL_EN_WID 1
/* 0: no data input 1: common data input */
#define COMMON_DATA_IN_EN_BIT 4
#define COMMON_DATA_IN_EN_WID 1
/* 1: MPEG, 2: 656, 3: TVFE, 4: CVD2, 5: HDMI_Rx,6: DVIN otherwise: NULL
*7: loopback from VIU1, 8: MIPI csi2 in meson6
*/
*7: loopback from VIU1, 8: MIPI csi2 in meson6
*/
#define VDIN_SEL_BIT 0
#define VDIN_SEL_WID 4
/* #define VDIN_ACTIVE_MAX_PIX_CNT_STATUS 0x1203 */
/* ~field_hold & prehsc input active max pixel
* every line output of window
@@ -820,8 +831,9 @@
#define WIDTHM1O_WID 13
/* #define VDIN_SC_MISC_CTRL 0x120b */
/* signed value for short line output
*/
/* signed value for short line output */
#define PRE_HSCL_MODE_BIT 17
#define PRE_HSCL_MODE_WID 4
#define INIT_PIX_IN_PTR_BIT 8
#define INIT_PIX_IN_PTR_WID 7
#define INIT_PIX_IN_PTR_MSK 0x0000007f
@@ -832,7 +844,7 @@
#define HSCL_EN_WID 1 /* hscaler: fine scale down */
#define SHORT_LN_OUT_EN_BIT 5
#define SHORT_LN_OUT_EN_WID 1
/* when decimation timing located in between 2 input pixels,
/*when decimation timing located in between 2 input pixels,
* decimate the nearest one
*/
#define HSCL_NEAREST_EN_BIT 4
@@ -852,8 +864,7 @@
#define HSCL_PHASE_STEP_FRA_WID 24
/* #define VDIN_HSC_INI_CTRL 0x120d */
/* repeatedly decimation of pixel #0 of each line?
*/
/* repeatedly decimation of pixel #0 of each line? */
#define HSCL_RPT_P0_NUM_BIT 29
#define HSCL_RPT_P0_NUM_WID 2
/* if rev>rpt_p0+1, then start decimation upon ini_phase? */
@@ -866,7 +877,6 @@
/* #define VDIN_COM_STATUS2 0x120e */
/* Read only */
#define VDI7_FIFO_OVFL_BIT 23 /* vdi7 fifo overflow */
#define VDI7_FIFO_OVFL_WID 1
#define VDI7_ASFIFO_CNT_BIT 16 /* vdi7_asfifo_cnt */
@@ -881,8 +891,6 @@
#define VDI5_ASFIFO_CNT_BIT 0 /* vdi5_asfifo_cnt */
#define VDI5_ASFIFO_CNT_WID 6
/* #define VDIN_ASFIFO_CTRL2 0x120f */
#define ASFIFO_DECIMATION_SYNC_WITH_DE_BIT 25
#define ASFIFO_DECIMATION_SYNC_WITH_DE_WID 1
@@ -914,7 +922,6 @@
/* write 1 & then 0 to reset */
#define ASFIFO5_SOFT_RST_WID 1
/* #define VDIN_MATRIX_CTRL 0x1210 */
#define VDIN_MATRIX0_BYPASS_BIT 9/* 1:bypass 0:pass */
#define VDIN_MATRIX0_BYPASS_WID 1
@@ -1017,17 +1024,38 @@
#define VDIN_INTF_WIDTHM1_BIT 0
#define VDIN_INTF_WIDTHM1_WID 13
/* #define VDIN_LFIFO_URG_CTRL 0x121e */
/*Bit 15 default== 0, urgent_ctrl_en
*Bit 14 default== 0, urgent_wr, if true for write buffer
*Bit 13 default== 0, out_inv_en
*Bit 12 default == 0, urgent_ini_value
*Bit 11:6 default == 0, up_th up threshold
*Bit 5:0 default == 0, dn_th dn threshold
*/
#define VDIN_LFIFO_URG_CTRL_EN_BIT 15
#define VDIN_LFIFO_URG_CTRL_EN_WID 1
#define VDIN_LFIFO_URG_WR_EN_BIT 14
#define VDIN_LFIFO_URG_WR_EN_WID 1
#define VDIN_LFIFO_OUT_INV_EN_BIT 13
#define VDIN_LFIFO_OUT_INV_EN_WID 1
#define VDIN_LFIFO_URG_INI_BIT 12
#define VDIN_LFIFO_URG_INI_WID 1
#define VDIN_LFIFO_URG_UP_TH_BIT 6
#define VDIN_LFIFO_URG_UP_TH_WID 6
#define VDIN_LFIFO_URG_DN_TH_BIT 0
#define VDIN_LFIFO_URG_DN_TH_WID 6
/* #define VDIN_WR_CTRL2 0x121f */
/*1: enable WR 10 bit mode, 0: disable WR 10 bit mode */
/*1: enable WR 10 bit mode, 0: disable WR 10 bit mode*/
#define VDIN_WR_10BIT_MODE_BIT 19
#define VDIN_WR_10BIT_MODE_WID 1
/* data_ext_en 1:send out data if req was interrupt by soft reset */
/* 0:normal mode */
#define VDIN_WR_DATA_EXT_EN_BIT 18
#define VDIN_WR_DATA_EXT_EN_WID 1
/* 0: 1 word in 1burst, 1: 2 words in 1burst;
* 10: 4 words in 1burst; 11: reserved
/*0: 1 word in 1burst, 1: 2 words in 1burst;
*10: 4 words in 1burst; 11: reserved
*/
#define VDIN_WR_BURST_MODE_BIT 12
#define VDIN_WR_BURST_MODE_WID 4
@@ -1093,8 +1121,6 @@
#define WR_CANVAS_BIT 0
#define WR_CANVAS_WID 8
/* #define VDIN_WR_H_START_END 0x1221 */
#define HORIZONTAL_REVERSE_BIT 29/* if true horizontal reverse */
@@ -1132,7 +1158,11 @@
/* #define VDIN_SCIN_HEIGHTM1 0x1225 */
/* Bit 12:0, scaler input height minus 1 */
#define SCALER_INPUT_HEIGHT_BIT 0
#define SCALER_INPUT_HEIGHT_WID 12
#define SCALER_INPUT_HEIGHT_WID 13
/* Bit 28:16, vshrk input height minus 1 */
#define VSHRK_INPUT_HEIGHT_BIT 16
#define VSHRK_INPUT_HEIGHT_WID 13
/* #define `define VDIN_DUMMY_DATA 0x1226 */
#define DUMMY_COMPONENT0_BIT 16
@@ -1549,7 +1579,6 @@
#define MEAS_VS_TOTAL_CNT_LO_BIT 0 /* vsync_total_counter[31:0] */
#define MEAS_VS_TOTAL_CNT_LO_WID 32
/* 1st/2nd/3rd/4th hs range according to VDIN_MEAS_HS_INDEX */
/* #define VDIN_MEAS_HS_RANGE 0x125d */
#define MEAS_HS_RANGE_CNT_START_BIT 16
@@ -1557,24 +1586,19 @@
#define MEAS_HS_RANGE_CNT_END_BIT 0
#define MEAS_HS_RANGE_CNT_END_WID 13
/* hs count as per 1st/2nd/3rd/4th hs range according to VDIN_MEAS_HS_INDEX */
/* #define VDIN_MEAS_HS_COUNT 0x125e // read only */
#define MEAS_HS_CNT_BIT 0
#define MEAS_HS_CNT_WID 24
/* #define VDIN_BLKBAR_CTRL1 0x125f */
#define BLKBAR_WHITE_EN_BIT 8
#define BLKBAR_WHITE_EN_WID 1
#define BLKBAR_WHITE_LVL_BIT 0
#define BLKBAR_WHITE_LVL_WID 8
/* #define VDIN_BLKBAR_CTRL0 0x1260 */
/* threshold to judge a black point */
#define BLKBAR_BLK_LVL_BIT 24
#define BLKBAR_BLK_LVL_WID 8
@@ -1586,7 +1610,7 @@
#define BLKBAR_COMP_SEL_BIT 5
#define BLKBAR_COMP_SEL_WID 3
/* sw statistic of black pixels of each block,
* 1: search once, 0: search continuously till the exact edge
*1: search once, 0: search continuously till the exact edge
*/
#define BLKBAR_SW_STAT_EN_BIT 4
#define BLKBAR_SW_STAT_EN_WID 1
@@ -1678,15 +1702,12 @@
#define INPUT_WIN_H_END_BIT 0
#define INPUT_WIN_H_END_WID 13
/* #define VDIN_WIN_V_START_END 0x126e */
#define INPUT_WIN_V_START_BIT 16
#define INPUT_WIN_V_START_WID 13
#define INPUT_WIN_V_END_BIT 0
#define INPUT_WIN_V_END_WID 13
/* Bit 15:8 vdi7 asfifo_ctrl */
/* Bit 7:0 vdi6 asfifo_ctrl */
/* #define VDIN_ASFIFO_CTRL3 0x126f */
@@ -1699,6 +1720,13 @@
#define VDI6_ASFIFO_CTRL_BIT 0
#define VDI6_ASFIFO_CTRL_WID 8
#define VDIN_VSHRK_EN_BIT 27
#define VDIN_VSHRK_EN_WID 1
#define VDIN_VSHRK_LPF_MODE_BIT 24
#define VDIN_VSHRK_LPF_MODE_WID 1
#define VDIN_VSHRK_MODE_BIT 25
#define VDIN_VSHRK_MODE_WID 2
/* Bit 3:2 vshrk_clk2_ctrl */
/* Bit 1:0 vshrk_clk1_ctrl */
/* #define VDIN_COM_GCLK_CTRL2 ((0x1270 << 2) + 0xd0100000) */
@@ -1713,7 +1741,34 @@
/* Bit 5:0, vdi9_asfifo_cnt */
/* #define VDIN_COM_STATUS3 ((0x1273 << 2) + 0xd0100000) */
#define VDIN_FORCEGOLINE_EN_BIT 28
#define VDIN_WRREQUEST_EN_BT 8
#define VDIN_WRCTRLREG_PAUSE_BIT 10
/*#define VDIN_INTF_WIDTHM1*/
#define VDIN_FIX_NONSTDVSYNC_BIT 24
#define VDIN_FIX_NONSTDVSYNC_WID 2
/*#define VPU_ARB_URG_CTRL*/
#define VDIN_LFF_URG_CTRL_BIT 8
#define VDIN_LFF_URG_CTRL_WID 1
#define VPP_OFF_URG_CTRL_BIT 6
#define VPP_OFF_URG_CTRL_WID 1
/*#define VDIN_COM_CTRL0*/
#define VDIN_COMMONINPUT_EN_BIT 4
#define VDIN_COMMONINPUT_EN_WID 1
/*#define VDIN_WR_CTRL*/
#define VDIN0_VCP_WR_EN_BIT 25
#define VDIN0_VCP_WR_EN_WID 1
#define VDIN0_DISABLE_CLOCKGATE_BIT 29
#define VDIN0_DISABLE_CLOCKGATE_WID 1
/*#define VDIN1_WR_CTRL*/
#define VDIN1_VCP_WR_EN_BIT 8
#define VDIN1_VCP_WR_EN_WID 1
#define VDIN1_DISABLE_CLOCKGATE_BIT 29
#define VDIN1_DISABLE_CLOCKGATE_WID 1
#endif /* __VDIN_REGS_H */

287
drivers/amlogic/media/vin/tvin/vdin/vdin_sm.c
View File

@@ -31,41 +31,26 @@
#include "vdin_ctl.h"
#include "vdin_drv.h"
/* Stay in TVIN_SIG_STATE_NOSIG for some
* cycles => be sure TVIN_SIG_STATE_NOSIG
*/
#define NOSIG_MAX_CNT 8
#define NOSIG_MAX_CNT 8
/* Stay in TVIN_SIG_STATE_UNSTABLE for some
* cycles => be sure TVIN_SIG_STATE_UNSTABLE
*/
#define UNSTABLE_MAX_CNT 2/* 4 */
#define UNSTABLE_MAX_CNT 2/* 4 */
/* Have signal for some cycles => exit TVIN_SIG_STATE_NOSIG */
#define EXIT_NOSIG_MAX_CNT 2/* 1 */
#define EXIT_NOSIG_MAX_CNT 2/* 1 */
/* No signal for some cycles => back to TVAFE_STATE_NOSIG */
#define BACK_NOSIG_MAX_CNT 24 /* 8 */
#define BACK_NOSIG_MAX_CNT 24 /* 8 */
/* Signal unstable for some cycles => exit TVAFE_STATE_STABLE */
#define EXIT_STABLE_MAX_CNT 1
#define EXIT_STABLE_MAX_CNT 1
/* Signal stable for some cycles => back to TVAFE_STATE_STABLE */
/* must >=500ms,for new api function */
#define BACK_STABLE_MAX_CNT 50
#define EXIT_PRESTABLE_MAX_CNT 50
/* must >=500ms,for new api function */
#define BACK_STABLE_MAX_CNT 50
#define EXIT_PRESTABLE_MAX_CNT 50
static struct tvin_sm_s sm_dev[VDIN_MAX_DEVS];
#if 0
/* TVIN_SIG_STATUS_NOSIG; */
static enum tvin_sm_status_e state = TVIN_SM_STATUS_NULL;
static unsigned int state_cnt; /* STATE_NOSIG, STATE_UNSTABLE */
static unsigned int exit_nosig_cnt; /* STATE_NOSIG */
static unsigned int back_nosig_cnt; /* STATE_UNSTABLE */
static unsigned int back_stable_cnt; /* STATE_UNSTABLE */
static unsigned int exit_prestable_cnt; /* STATE_PRESTABLE */
#endif
static bool sm_debug_enable = true;
static int sm_print_nosig;
static int sm_print_notsup;
static int sm_print_unstable;
@@ -74,96 +59,87 @@ static int sm_print_fmt_chg;
static int sm_atv_prestable_fmt;
static int sm_print_prestable;
static bool sm_debug_enable = true;
module_param(sm_debug_enable, bool, 0664);
MODULE_PARM_DESC(sm_debug_enable,
"enable/disable state machine debug message");
#if 1
static int back_nosig_max_cnt = BACK_NOSIG_MAX_CNT;
module_param(back_nosig_max_cnt, int, 0664);
MODULE_PARM_DESC(back_nosig_max_cnt,
"unstable enter nosignal state max count");
static int atv_unstable_in_cnt = 45;
module_param(atv_unstable_in_cnt, int, 0664);
MODULE_PARM_DESC(atv_unstable_in_cnt, "atv_unstable_in_cnt");
static int atv_unstable_out_cnt = 50;
module_param(atv_unstable_out_cnt, int, 0664);
MODULE_PARM_DESC(atv_unstable_out_cnt, "atv_unstable_out_cnt");
static int hdmi_unstable_out_cnt = 20;
module_param(hdmi_unstable_out_cnt, int, 0664);
MODULE_PARM_DESC(hdmi_unstable_out_cnt, "hdmi_unstable_out_cnt");
static int hdmi_unstable_out_cnt = 1;
static int hdmi_stable_out_cnt = 1;/* 25; */
module_param(hdmi_stable_out_cnt, int, 0664);
MODULE_PARM_DESC(hdmi_stable_out_cnt, "hdmi_stable_out_cnt");
/* new add in gxtvbb@20160523,reason:
*gxtvbb add atv snow config,the config will affect signal detect.
*if atv_stable_out_cnt < 100,the signal state will change
*after swich source to atv or after atv search
*/
static int atv_stable_out_cnt = 100;
module_param(atv_stable_out_cnt, int, 0664);
MODULE_PARM_DESC(atv_stable_out_cnt, "atv_stable_out_cnt");
/* new add in gxtvbb@20160613,reason:
*gxtvbb add atv snow config,the config will affect signal detect.
*ensure after fmt change,the new fmt can be detect in time!
*/
static int atv_stable_fmt_check_cnt = 10;
module_param(atv_stable_fmt_check_cnt, int, 0664);
MODULE_PARM_DESC(atv_stable_fmt_check_cnt, "atv_stable_fmt_check_cnt");
/* new add in gxtvbb@20160613,reason:
* ensure vdin fmt can update when fmt is changed in menu
*/
static int atv_stable_fmt_check_enable;
/* new add in gxtvbb@20160523,reason:
*gxtvbb add atv snow config,the config will affect signal detect.
*ensure after prestable into stable,the state is really stable!
*/
static int atv_prestable_out_cnt = 100;
static int other_stable_out_cnt = EXIT_STABLE_MAX_CNT;
static int other_unstable_out_cnt = BACK_STABLE_MAX_CNT;
static int other_unstable_in_cnt = UNSTABLE_MAX_CNT;
static int nosig_in_cnt = NOSIG_MAX_CNT;
static int nosig2_unstable_cnt = EXIT_NOSIG_MAX_CNT;
#ifdef DEBUG_SUPPORT
module_param(back_nosig_max_cnt, int, 0664);
MODULE_PARM_DESC(back_nosig_max_cnt,
"unstable enter nosignal state max count");
module_param(atv_unstable_in_cnt, int, 0664);
MODULE_PARM_DESC(atv_unstable_in_cnt, "atv_unstable_in_cnt");
module_param(atv_unstable_out_cnt, int, 0664);
MODULE_PARM_DESC(atv_unstable_out_cnt, "atv_unstable_out_cnt");
module_param(hdmi_unstable_out_cnt, int, 0664);
MODULE_PARM_DESC(hdmi_unstable_out_cnt, "hdmi_unstable_out_cnt");
module_param(hdmi_stable_out_cnt, int, 0664);
MODULE_PARM_DESC(hdmi_stable_out_cnt, "hdmi_stable_out_cnt");
module_param(atv_stable_out_cnt, int, 0664);
MODULE_PARM_DESC(atv_stable_out_cnt, "atv_stable_out_cnt");
module_param(atv_stable_fmt_check_cnt, int, 0664);
MODULE_PARM_DESC(atv_stable_fmt_check_cnt, "atv_stable_fmt_check_cnt");
module_param(atv_prestable_out_cnt, int, 0664);
MODULE_PARM_DESC(atv_prestable_out_cnt, "atv_prestable_out_cnt");
static int other_stable_out_cnt = EXIT_STABLE_MAX_CNT;
module_param(other_stable_out_cnt, int, 0664);
MODULE_PARM_DESC(other_stable_out_cnt, "other_stable_out_cnt");
static int other_unstable_out_cnt = BACK_STABLE_MAX_CNT;
module_param(other_unstable_out_cnt, int, 0664);
MODULE_PARM_DESC(other_unstable_out_cnt, "other_unstable_out_cnt");
static int other_unstable_in_cnt = UNSTABLE_MAX_CNT;
module_param(other_unstable_in_cnt, int, 0664);
MODULE_PARM_DESC(other_unstable_in_cnt, "other_unstable_in_cnt");
static int comp_pre2_stable_cnt = EXIT_PRESTABLE_MAX_CNT;
module_param(comp_pre2_stable_cnt, int, 0664);
MODULE_PARM_DESC(comp_pre2_stable_cnt, "comp_pre2_stable_cnt");
static int nosig_in_cnt = NOSIG_MAX_CNT;
module_param(nosig_in_cnt, int, 0664);
MODULE_PARM_DESC(nosig_in_cnt, "nosig_in_cnt");
static int nosig2_unstable_cnt = EXIT_NOSIG_MAX_CNT;
module_param(nosig2_unstable_cnt, int, 0664);
MODULE_PARM_DESC(nosig2_unstable_cnt, "nosig2_unstable_cnt");
/*
* void tvin_smr_init_counter(void)
* {
* state_cnt = 0;
* exit_nosig_cnt = 0;
* back_nosig_cnt = 0;
* back_stable_cnt = 0;
* exit_prestable_cnt = 0;
* }
*/
#endif
static int signal_status = TVIN_SIG_STATUS_NULL;
module_param(signal_status, int, 0664);
MODULE_PARM_DESC(signal_status, "signal_status");
/*
* check hdmirx color format
*/
@@ -172,6 +148,7 @@ static void hdmirx_color_fmt_handler(struct vdin_dev_s *devp)
struct tvin_state_machine_ops_s *sm_ops;
enum tvin_port_e port = TVIN_PORT_NULL;
enum tvin_color_fmt_e cur_color_fmt, pre_color_fmt;
enum tvin_color_fmt_e cur_dest_color_fmt, pre_dest_color_fmt;
struct tvin_sig_property_s *prop, *pre_prop;
unsigned int vdin_hdr_flag, pre_vdin_hdr_flag;
unsigned int vdin_fmt_range, pre_vdin_fmt_range;
@@ -198,6 +175,9 @@ static void hdmirx_color_fmt_handler(struct vdin_dev_s *devp)
cur_color_fmt = prop->color_format;
pre_color_fmt = pre_prop->color_format;
cur_dest_color_fmt = prop->dest_cfmt;
pre_dest_color_fmt = pre_prop->dest_cfmt;
vdin_hdr_flag = prop->vdin_hdr_Flag;
pre_vdin_hdr_flag = pre_prop->vdin_hdr_Flag;
@@ -206,12 +186,14 @@ static void hdmirx_color_fmt_handler(struct vdin_dev_s *devp)
if ((cur_color_fmt != pre_color_fmt) ||
(vdin_hdr_flag != pre_vdin_hdr_flag) ||
(vdin_fmt_range != pre_vdin_fmt_range)
) {
pr_info("[smr.%d] color fmt(%d->%d),csc_cfg:0x%x\n",
devp->index,
pre_color_fmt, cur_color_fmt,
devp->csc_cfg);
(vdin_fmt_range != pre_vdin_fmt_range) ||
(cur_dest_color_fmt != pre_dest_color_fmt)) {
pr_info("[smr.%d] cur color fmt(%d->%d), hdr_flag(%d->%d), dest color fmt(%d->%d), csc_cfg:0x%x\n",
devp->index,
pre_color_fmt, cur_color_fmt,
pre_vdin_hdr_flag, vdin_hdr_flag,
pre_dest_color_fmt, cur_dest_color_fmt,
devp->csc_cfg);
vdin_get_format_convert(devp);
devp->csc_cfg = 1;
} else
@@ -219,6 +201,48 @@ static void hdmirx_color_fmt_handler(struct vdin_dev_s *devp)
}
}
/* check auto de to adjust vdin cutwindow */
void vdin_auto_de_handler(struct vdin_dev_s *devp)
{
struct tvin_state_machine_ops_s *sm_ops;
struct tvin_sig_property_s *prop;
unsigned int cur_vs, cur_ve, pre_vs, pre_ve;
unsigned int cur_hs, cur_he, pre_hs, pre_he;
if (!devp) {
return;
} else if (!devp->frontend) {
sm_dev[devp->index].state = TVIN_SM_STATUS_NULL;
return;
}
if (devp->auto_cutwindow_en == 0)
return;
prop = &devp->prop;
sm_ops = devp->frontend->sm_ops;
if ((devp->flags & VDIN_FLAG_DEC_STARTED) &&
(sm_ops->get_sig_property)) {
sm_ops->get_sig_property(devp->frontend, prop);
cur_vs = prop->vs;
cur_ve = prop->ve;
cur_hs = prop->hs;
cur_he = prop->he;
pre_vs = prop->pre_vs;
pre_ve = prop->pre_ve;
pre_hs = prop->pre_hs;
pre_he = prop->pre_he;
if ((pre_vs != cur_vs) || (pre_ve != cur_ve) ||
(pre_hs != cur_hs) || (pre_he != cur_he)) {
pr_info("[smr.%d] pre_vs(%d->%d),pre_ve(%d->%d),pre_hs(%d->%d),pre_he(%d->%d),cutwindow_cfg:0x%x\n",
devp->index, pre_vs, cur_vs, pre_ve, cur_ve,
pre_hs, cur_hs, pre_he, cur_he,
devp->cutwindow_cfg);
devp->cutwindow_cfg = 1;
} else {
devp->cutwindow_cfg = 0;
}
}
}
void tvin_smr_init_counter(int index)
{
sm_dev[index].state_cnt = 0;
@@ -228,6 +252,16 @@ void tvin_smr_init_counter(int index)
sm_dev[index].exit_prestable_cnt = 0;
}
static void hdmirx_dv_check(struct vdin_dev_s *devp,
struct tvin_sig_property_s *prop)
{
/*check hdmiin dolby input*/
if (prop->dolby_vision != devp->dv.dv_flag) {
tvin_smr_init(devp->index);
devp->dv.dv_flag = prop->dolby_vision;
}
}
/*
* tvin state machine routine
*
@@ -235,7 +269,7 @@ void tvin_smr_init_counter(int index)
void tvin_smr(struct vdin_dev_s *devp)
{
struct tvin_state_machine_ops_s *sm_ops;
struct tvin_info_s *info, *pre_info;
struct tvin_info_s *info;
enum tvin_port_e port = TVIN_PORT_NULL;
unsigned int unstb_in;
struct tvin_sm_s *sm_p;
@@ -249,34 +283,32 @@ void tvin_smr(struct vdin_dev_s *devp)
return;
}
if (devp->flags & VDIN_FLAG_SM_DISABLE)
if ((devp->flags & VDIN_FLAG_SM_DISABLE) ||
(devp->flags & VDIN_FLAG_SUSPEND))
return;
sm_p = &sm_dev[devp->index];
fe = devp->frontend;
sm_ops = devp->frontend->sm_ops;
info = &devp->parm.info;
pre_info = &devp->pre_info;
port = devp->parm.port;
prop = &devp->prop;
pre_prop = &devp->pre_prop;
hdmirx_dv_check(devp, prop);
switch (sm_p->state) {
case TVIN_SM_STATUS_NOSIG:
++sm_p->state_cnt;
#ifdef CONFIG_AMLOGIC_MEDIA_TVAFE
if (port == TVIN_PORT_CVBS3)
tvafe_snow_config_clamp(1);
#endif
/*if ((port == TVIN_PORT_CVBS3) &&
* (devp->flags & VDIN_FLAG_SNOW_FLAG))
* tvafe_snow_config_clamp(1);
*/
if (sm_ops->nosig(devp->frontend)) {
sm_p->exit_nosig_cnt = 0;
if (sm_p->state_cnt >= nosig_in_cnt) {
sm_p->state_cnt = nosig_in_cnt;
info->status = TVIN_SIG_STATUS_NOSIG;
if (pre_info->status != info->status) {
pre_info->status = info->status;
queue_delayed_work(devp->sig_wq,
&devp->sig_dwork, 0);
}
info->fmt = TVIN_SIG_FMT_NULL;
if (sm_debug_enable && !sm_print_nosig) {
pr_info("[smr.%d] no signal\n",
@@ -308,11 +340,6 @@ void tvin_smr(struct vdin_dev_s *devp)
tvin_smr_init_counter(devp->index);
sm_p->state = TVIN_SM_STATUS_NOSIG;
info->status = TVIN_SIG_STATUS_NOSIG;
if (pre_info->status != info->status) {
pre_info->status = info->status;
queue_delayed_work(devp->sig_wq,
&devp->sig_dwork, 0);
}
info->fmt = TVIN_SIG_FMT_NULL;
if (sm_debug_enable)
pr_info("[smr.%d] unstable --> no signal\n",
@@ -326,7 +353,8 @@ void tvin_smr(struct vdin_dev_s *devp)
sm_p->back_stable_cnt = 0;
if (((port == TVIN_PORT_CVBS3) ||
(port == TVIN_PORT_CVBS0)) &&
devp->unstable_flag)
devp->unstable_flag &&
(devp->flags & VDIN_FLAG_SNOW_FLAG))
/* UNSTABLE_ATV_MAX_CNT; */
unstb_in = sm_p->atv_unstable_in_cnt;
else
@@ -334,11 +362,6 @@ void tvin_smr(struct vdin_dev_s *devp)
if (sm_p->state_cnt >= unstb_in) {
sm_p->state_cnt = unstb_in;
info->status = TVIN_SIG_STATUS_UNSTABLE;
if (pre_info->status != info->status) {
pre_info->status = info->status;
queue_delayed_work(devp->sig_wq,
&devp->sig_dwork, 0);
}
info->fmt = TVIN_SIG_FMT_NULL;
if (sm_debug_enable &&
!sm_print_unstable) {
@@ -350,8 +373,9 @@ void tvin_smr(struct vdin_dev_s *devp)
}
} else {
++sm_p->back_stable_cnt;
if ((port == TVIN_PORT_CVBS3) ||
(port == TVIN_PORT_CVBS0))
if (((port == TVIN_PORT_CVBS3) ||
(port == TVIN_PORT_CVBS0)) &&
(devp->flags & VDIN_FLAG_SNOW_FLAG))
unstb_in = sm_p->atv_unstable_out_cnt;
else if ((port >= TVIN_PORT_HDMI0) &&
(port <= TVIN_PORT_HDMI7))
@@ -368,25 +392,21 @@ void tvin_smr(struct vdin_dev_s *devp)
sm_ops->get_fmt(fe);
sm_ops->get_sig_property(fe,
prop);
info->cfmt = prop->color_format;
memcpy(pre_prop, prop,
sizeof(struct tvin_sig_property_s));
devp->parm.info.trans_fmt =
prop->trans_fmt;
devp->parm.info.reserved =
prop->dvi_info & 0xf;
devp->parm.info.is_dvi =
prop->dvi_info;
devp->parm.info.fps =
prop->dvi_info >> 4;
prop->fps;
}
} else
info->fmt = TVIN_SIG_FMT_NULL;
if (info->fmt == TVIN_SIG_FMT_NULL) {
/* remove unsupport status */
info->status = TVIN_SIG_STATUS_UNSTABLE;
if (pre_info->status != info->status) {
pre_info->status = info->status;
queue_delayed_work(devp->sig_wq,
&devp->sig_dwork, 0);
}
if (sm_debug_enable &&
!sm_print_notsup) {
pr_info("[smr.%d] unstable --> not support\n",
@@ -418,12 +438,11 @@ void tvin_smr(struct vdin_dev_s *devp)
case TVIN_SM_STATUS_PRESTABLE: {
bool nosig = false, fmt_changed = false;
unsigned int prestable_out_cnt = 0;
devp->unstable_flag = true;
#ifdef CONFIG_AMLOGIC_MEDIA_TVAFE
if (port == TVIN_PORT_CVBS3)
tvafe_snow_config_clamp(0);
#endif
/*if ((port == TVIN_PORT_CVBS3) &&
* (devp->flags & VDIN_FLAG_SNOW_FLAG))
* tvafe_snow_config_clamp(0);
*/
if (sm_ops->nosig(devp->frontend)) {
nosig = true;
if (sm_debug_enable && !(sm_print_prestable&0x1)) {
@@ -444,7 +463,8 @@ void tvin_smr(struct vdin_dev_s *devp)
if (nosig || fmt_changed) {
++sm_p->state_cnt;
if (port == TVIN_PORT_CVBS3)
if ((port == TVIN_PORT_CVBS3) &&
(devp->flags & VDIN_FLAG_SNOW_FLAG))
prestable_out_cnt = atv_prestable_out_cnt;
else
prestable_out_cnt = other_stable_out_cnt;
@@ -463,21 +483,18 @@ void tvin_smr(struct vdin_dev_s *devp)
} else {
sm_p->state_cnt = 0;
if (port == TVIN_PORT_CVBS3) {
if ((port == TVIN_PORT_CVBS3) &&
(devp->flags & VDIN_FLAG_SNOW_FLAG)) {
++sm_p->exit_prestable_cnt;
if (sm_p->exit_prestable_cnt <
atv_prestable_out_cnt)
break;
sm_p->exit_prestable_cnt = 0;
else
sm_p->exit_prestable_cnt = 0;
}
sm_p->state = TVIN_SM_STATUS_STABLE;
info->status = TVIN_SIG_STATUS_STABLE;
if (pre_info->status != info->status) {
pre_info->status = info->status;
queue_delayed_work(devp->sig_wq,
&devp->sig_dwork, 0);
}
if (sm_debug_enable)
pr_info("[smr.%d] %ums prestable --> stable\n",
devp->index,
@@ -492,8 +509,8 @@ void tvin_smr(struct vdin_dev_s *devp)
bool nosig = false, fmt_changed = false;
unsigned int stable_out_cnt = 0;
unsigned int stable_fmt = 0;
devp->unstable_flag = true;
if (sm_ops->nosig(devp->frontend)) {
nosig = true;
if (sm_debug_enable && !sm_print_fmt_nosig) {
@@ -511,6 +528,13 @@ void tvin_smr(struct vdin_dev_s *devp)
sm_print_fmt_chg = 1;
}
}
/* dynamic adjust cutwindow for atv test */
if ((port >= TVIN_PORT_CVBS0) &&
(port <= TVIN_PORT_CVBS7))
vdin_auto_de_handler(devp);
if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_CVBS7) &&
devp->auto_ratio_en && sm_ops->get_sig_property)
sm_ops->get_sig_property(devp->frontend, prop);
/* hdmirx_color_fmt_handler(devp); */
#if 0
if (sm_ops->pll_lock(devp->frontend)) {
@@ -524,8 +548,9 @@ void tvin_smr(struct vdin_dev_s *devp)
if (nosig || fmt_changed /* || !pll_lock */) {
++sm_p->state_cnt;
if ((port == TVIN_PORT_CVBS3) ||
(port == TVIN_PORT_CVBS0))
if (((port == TVIN_PORT_CVBS3) ||
(port == TVIN_PORT_CVBS0)) &&
(devp->flags & VDIN_FLAG_SNOW_FLAG))
stable_out_cnt = sm_p->atv_stable_out_cnt;
else if ((port >= TVIN_PORT_HDMI0) &&
(port <= TVIN_PORT_HDMI7))
@@ -534,7 +559,8 @@ void tvin_smr(struct vdin_dev_s *devp)
stable_out_cnt = other_stable_out_cnt;
/*add for atv snow*/
if ((sm_p->state_cnt >= atv_stable_fmt_check_cnt) &&
(port == TVIN_PORT_CVBS3))
(port == TVIN_PORT_CVBS3) &&
(devp->flags & VDIN_FLAG_SNOW_FLAG))
atv_stable_fmt_check_enable = 1;
if (sm_p->state_cnt >= stable_out_cnt) {
tvin_smr_init_counter(devp->index);
@@ -554,6 +580,7 @@ void tvin_smr(struct vdin_dev_s *devp)
/*add for atv snow*/
if ((port == TVIN_PORT_CVBS3) &&
atv_stable_fmt_check_enable &&
(devp->flags & VDIN_FLAG_SNOW_FLAG) &&
(sm_ops->get_fmt && sm_ops->get_sig_property)) {
sm_p->state_cnt = 0;
stable_fmt =
@@ -565,10 +592,10 @@ void tvin_smr(struct vdin_dev_s *devp)
sizeof(struct tvin_sig_property_s));
devp->parm.info.trans_fmt =
prop->trans_fmt;
devp->parm.info.reserved =
prop->dvi_info & 0xf;
devp->parm.info.is_dvi =
prop->dvi_info;
devp->parm.info.fps =
prop->dvi_info >> 4;
prop->fps;
info->fmt = stable_fmt;
atv_stable_fmt_check_enable = 0;
if (sm_debug_enable)
@@ -589,6 +616,11 @@ void tvin_smr(struct vdin_dev_s *devp)
sm_p->state = TVIN_SM_STATUS_NOSIG;
break;
}
if (sm_p->sig_status != info->status) {
sm_p->sig_status = info->status;
wake_up(&devp->queue);
}
signal_status = sm_p->sig_status;
}
/*
@@ -598,6 +630,7 @@ void tvin_smr(struct vdin_dev_s *devp)
void tvin_smr_init(int index)
{
sm_dev[index].sig_status = TVIN_SIG_STATUS_NULL;
sm_dev[index].state = TVIN_SM_STATUS_NULL;
sm_dev[index].atv_stable_out_cnt = atv_stable_out_cnt;
sm_dev[index].atv_unstable_in_cnt = atv_unstable_in_cnt;

1
drivers/amlogic/media/vin/tvin/vdin/vdin_sm.h
View File

@@ -35,6 +35,7 @@ enum tvin_sm_status_e {
TVIN_SM_STATUS_STABLE,
};
struct tvin_sm_s {
enum tvin_sig_status_e sig_status;
enum tvin_sm_status_e state;
unsigned int state_cnt; /* STATE_NOSIG, STATE_UNSTABLE */
unsigned int exit_nosig_cnt; /* STATE_NOSIG */

8
drivers/amlogic/media/vin/tvin/vdin/vdin_v4l2.c
View File

@@ -61,10 +61,16 @@ struct vdin_v4l2_ops_s *get_vdin_v4l2_ops()
{
if ((ops.start_tvin_service != NULL) && (ops.stop_tvin_service != NULL))
return &ops;
return NULL;
else {
/* pr_err("[vdin..]%s: vdin v4l2 operation
* haven't registered.",__func__);
*/
return NULL;
}
}
EXPORT_SYMBOL(get_vdin_v4l2_ops);
/*Converts commands into strings */
const char *cam_cmd_to_str(enum cam_command_e cmd)
{
switch (cmd) {

133
drivers/amlogic/media/vin/tvin/vdin/vdin_vf.c
View File

@@ -33,7 +33,7 @@
/* Local Headers */
#include "vdin_vf.h"
#include "vdin_ctl.h"
static bool vf_log_enable = true;
static bool vf_log_fe = true;
static bool vf_log_be = true;
@@ -47,7 +47,6 @@ MODULE_PARM_DESC(vf_log_fe, "enable/disable vframe manager log frontend");
module_param(vf_log_be, bool, 0664);
MODULE_PARM_DESC(vf_log_be, "enable/disable vframe manager log backen");
#ifdef VF_LOG_EN
void vf_log_init(struct vf_pool *p)
{
@@ -146,8 +145,8 @@ void vf_log_print(struct vf_pool *p)
{
unsigned int i = 0, j = 0, k = 0;
int len = 0;
char buf1[100];
char buf2[100];
char buf1[VF_LOG_PRINT_MAX_LEN];
char buf2[VF_LOG_PRINT_MAX_LEN];
struct vf_log_s *log = &p->log;
pr_info("%-10s %-10s %-10s %-10s %-10s %-10s %5s\n",
@@ -316,6 +315,8 @@ struct vf_pool *vf_pool_alloc(int size)
spin_lock_init(&p->wt_lock);
spin_lock_init(&p->fz_lock);
spin_lock_init(&p->tmp_lock);
spin_lock_init(&p->log_lock);
spin_lock_init(&p->dv_lock);
/* initialize list head */
INIT_LIST_HEAD(&p->wr_list);
INIT_LIST_HEAD(&p->rd_list);
@@ -380,6 +381,7 @@ int vf_pool_init(struct vf_pool *p, int size)
p->tmp_list_size = 0;
/* initialize provider write list */
for (i = 0; i < size; i++) {
p->dv_buf_size[i] = 0;
master = vf_get_master(p, i);
if (master == NULL) {
log_state = false;
@@ -403,9 +405,18 @@ int vf_pool_init(struct vf_pool *p, int size)
slave->status = VF_STATUS_SL;
}
atomic_set(&p->buffer_cnt, 0);
for (i = 0; i < VFRAME_DISP_MAX_NUM; i++) {
if (p->skip_vf_num == 0)
p->disp_mode[i] = VFRAME_DISP_MODE_NULL;
else
p->disp_mode[i] = VFRAME_DISP_MODE_UNKNOWN;
p->disp_index[i] = 0;
}
#ifdef VF_LOG_EN
spin_lock_irqsave(&p->log_lock, flags);
vf_log_init(p);
vf_log(p, VF_OPERATION_INIT, log_state);
spin_unlock_irqrestore(&p->log_lock, flags);
#endif
return 0;
}
@@ -414,8 +425,12 @@ int vf_pool_init(struct vf_pool *p, int size)
/* free the vframe pool of the vfp */
void vf_pool_free(struct vf_pool *p)
{
unsigned long flags;
if (p) {
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_FREE, true);
spin_unlock_irqrestore(&p->log_lock, flags);
/* if (p->master) */
kfree(p->master);
/* if (p->slave) */
@@ -453,8 +468,8 @@ static inline void vf_pool_put(struct vf_entry *vfe, struct list_head *head)
list_add(&vfe->list, head);
}
/*
*move all vf_entrys in tmp list to writable list
*/
*move all vf_entrys in tmp list to writable list
*/
void recycle_tmp_vfs(struct vf_pool *p)
{
struct vf_entry *pos = NULL, *tmp = NULL;
@@ -469,8 +484,8 @@ void recycle_tmp_vfs(struct vf_pool *p)
spin_unlock_irqrestore(&p->tmp_lock, flags);
}
/*
*put vf_entry to tmp list
*/
*put vf_entry to tmp list
*/
void tmp_vf_put(struct vf_entry *vfe, struct vf_pool *p)
{
unsigned long flags;
@@ -481,8 +496,8 @@ void tmp_vf_put(struct vf_entry *vfe, struct vf_pool *p)
spin_unlock_irqrestore(&p->tmp_lock, flags);
}
/*
*move all vf_entry in tmp list to readable list
*/
*move all vf_entry in tmp list to readable list
*/
void tmp_to_rd(struct vf_pool *p)
{
struct vf_entry *pos = NULL, *tmp = NULL;
@@ -504,10 +519,12 @@ struct vf_entry *provider_vf_peek(struct vf_pool *p)
spin_lock_irqsave(&p->wr_lock, flags);
vfe = vf_pool_peek(&p->wr_list);
spin_unlock_irqrestore(&p->wr_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
if (!vfe)
vf_log(p, VF_OPERATION_FPEEK, false);
else
vf_log(p, VF_OPERATION_FPEEK, true);
spin_unlock_irqrestore(&p->log_lock, flags);
return vfe;
}
@@ -521,12 +538,16 @@ struct vf_entry *provider_vf_get(struct vf_pool *p)
vfe = vf_pool_get(&p->wr_list);
spin_unlock_irqrestore(&p->wr_lock, flags);
if (!vfe) {
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_FGET, false);
spin_unlock_irqrestore(&p->log_lock, flags);
return NULL;
}
spin_lock_irqsave(&p->log_lock, flags);
p->wr_list_size--;
vfe->status = VF_STATUS_WM;
vf_log(p, VF_OPERATION_FGET, true);
spin_unlock_irqrestore(&p->log_lock, flags);
return vfe;
}
@@ -539,7 +560,9 @@ void provider_vf_put(struct vf_entry *vfe, struct vf_pool *p)
vf_pool_put(vfe, &p->rd_list);
p->rd_list_size++;
spin_unlock_irqrestore(&p->rd_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_FPUT, true);
spin_unlock_irqrestore(&p->log_lock, flags);
}
/* receiver peek to read */
@@ -558,10 +581,12 @@ struct vf_entry *receiver_vf_peek(struct vf_pool *p)
spin_lock_irqsave(&p->rd_lock, flags);
vfe = vf_pool_peek(&p->rd_list);
spin_unlock_irqrestore(&p->rd_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
if (!vfe)
vf_log(p, VF_OPERATION_BPEEK, false);
else
vf_log(p, VF_OPERATION_BPEEK, true);
spin_unlock_irqrestore(&p->log_lock, flags);
if (!vfe)
return NULL;
return vfe;
@@ -572,6 +597,7 @@ struct vf_entry *receiver_vf_get(struct vf_pool *p)
{
struct vf_entry *vfe;
unsigned long flags;
/*get the vframe from the frozen list*/
if (p->pool_flag & VDIN_VF_POOL_FREEZE) {
spin_lock_irqsave(&p->fz_lock, flags);
@@ -587,7 +613,9 @@ struct vf_entry *receiver_vf_get(struct vf_pool *p)
spin_lock_irqsave(&p->rd_lock, flags);
if (list_empty(&p->rd_list)) {
spin_unlock_irqrestore(&p->rd_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BGET, false);
spin_unlock_irqrestore(&p->log_lock, flags);
return NULL;
}
@@ -595,12 +623,13 @@ struct vf_entry *receiver_vf_get(struct vf_pool *p)
p->rd_list_size--;
spin_unlock_irqrestore(&p->rd_lock, flags);
vfe->status = VF_STATUS_RM;
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BGET, true);
spin_unlock_irqrestore(&p->log_lock, flags);
return vfe;
}
/*check vf point,0:nornal;1:bad*/
unsigned int check_vf_put(struct vframe_s *vf, struct vf_pool *p)
static unsigned int check_vf_put(struct vframe_s *vf, struct vf_pool *p)
{
struct vf_entry *master;
unsigned int i;
@@ -626,11 +655,12 @@ void receiver_vf_put(struct vframe_s *vf, struct vf_pool *p)
return;
master = vf_get_master(p, vf->index);
if (master == NULL) {
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BPUT, false);
spin_unlock_irqrestore(&p->log_lock, flags);
return;
}
/*
* keep the frozen frame in rd list&recycle the
/*keep the frozen frame in rd list&recycle the
* frame which not in fz list when unfreeze
*/
if (master->flag & VF_FLAG_FREEZED_FRAME) {
@@ -652,7 +682,9 @@ void receiver_vf_put(struct vframe_s *vf, struct vf_pool *p)
vf_pool_put(master, &p->wr_list);
p->wr_list_size++;
spin_unlock_irqrestore(&p->wr_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BPUT, true);
spin_unlock_irqrestore(&p->log_lock, flags);
} else {
spin_lock_irqsave(&p->wt_lock, flags);
list_for_each_entry_safe(pos, tmp, &p->wt_list, list) {
@@ -675,7 +707,9 @@ void receiver_vf_put(struct vframe_s *vf, struct vf_pool *p)
slave = vf_get_slave(p, vf->index);
if (slave == NULL) {
spin_unlock_irqrestore(&p->wt_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BPUT, false);
spin_unlock_irqrestore(&p->log_lock, flags);
return;
}
/* if found associated entry in wait list */
@@ -692,7 +726,9 @@ void receiver_vf_put(struct vframe_s *vf, struct vf_pool *p)
p->wr_list_size++;
spin_unlock_irqrestore(&p->wr_lock, flags);
slave->status = VF_STATUS_SL;
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BPUT, true);
spin_unlock_irqrestore(&p->log_lock, flags);
} else {
/* if not found associated entry in wait list */
@@ -712,7 +748,9 @@ void receiver_vf_put(struct vframe_s *vf, struct vf_pool *p)
list_add(&master->list, &p->wt_list);
}
spin_unlock_irqrestore(&p->wt_lock, flags);
spin_lock_irqsave(&p->log_lock, flags);
vf_log(p, VF_OPERATION_BPUT, true);
spin_unlock_irqrestore(&p->log_lock, flags);
}
}
atomic_dec(&p->buffer_cnt);
@@ -755,6 +793,13 @@ void vdin_vf_put(struct vframe_s *vf, void *op_arg)
return;
p = (struct vf_pool *)op_arg;
receiver_vf_put(vf, p);
/*clean dv-buf-size*/
if (vf && (dv_dbg_mask & DV_CLEAN_UP_MEM)) {
p->dv_buf_size[vf->index] = 0;
if (p->dv_buf_ori[vf->index])
memset(p->dv_buf_ori[vf->index], 0, dolby_size_byte);
}
}
int vdin_vf_states(struct vframe_states *vf_ste, void *op_arg)
{
@@ -771,9 +816,9 @@ int vdin_vf_states(struct vframe_states *vf_ste, void *op_arg)
}
/*
* hold the buffer from rd list,if rd list is not enough,
* get buffer from wr list
*/
*hold the buffer from rd list,if rd list is not enough,
*get buffer from wr list
*/
void vdin_vf_freeze(struct vf_pool *p, unsigned int num)
{
struct vf_entry *vfe, *tmp;
@@ -843,7 +888,7 @@ void vdin_vf_unfreeze(struct vf_pool *p)
spin_unlock_irqrestore(&p->fz_lock, flags);
}
}
/*dump vframe state*/
void vdin_dump_vf_state(struct vf_pool *p)
{
unsigned long flags;
@@ -852,42 +897,78 @@ void vdin_dump_vf_state(struct vf_pool *p)
pr_info("buffers in writeable list:\n");
spin_lock_irqsave(&p->wr_lock, flags);
list_for_each_entry_safe(pos, tmp, &p->wr_list, list) {
pr_info("\t index: %2u,status %u, canvas index0: 0x%x,",
pr_info("index: %2u,status %u, canvas index0: 0x%x,",
pos->vf.index, pos->status, pos->vf.canvas0Addr);
pr_info("index1: 0x%x, vframe type: 0x%x.\n",
pr_info("\t canvas index1: 0x%x, vframe type: 0x%x.\n",
pos->vf.canvas1Addr, pos->vf.type);
pr_info("\t ratio_control(0x%x).\n", pos->vf.ratio_control);
}
spin_unlock_irqrestore(&p->wr_lock, flags);
pr_info("buffer in readable list:\n");
spin_lock_irqsave(&p->rd_lock, flags);
list_for_each_entry_safe(pos, tmp, &p->rd_list, list) {
pr_info("\t index: %u,status %u, canvas index0: 0x%x,",
pr_info("index: %u,status %u, canvas index0: 0x%x,",
pos->vf.index, pos->status, pos->vf.canvas0Addr);
pr_info("index1: 0x%x, vframe type: 0x%x.\n",
pr_info("\t canvas index1: 0x%x, vframe type: 0x%x.\n",
pos->vf.canvas1Addr, pos->vf.type);
pr_info("\t ratio_control(0x%x).\n", pos->vf.ratio_control);
}
spin_unlock_irqrestore(&p->rd_lock, flags);
pr_info("buffer in waiting list:\n");
spin_lock_irqsave(&p->wt_lock, flags);
list_for_each_entry_safe(pos, tmp, &p->wt_list, list) {
pr_info("\t index: %u, status %u, canvas index0: 0x%x,",
pr_info("index: %u, status %u, canvas index0: 0x%x,",
pos->vf.index, pos->status, pos->vf.canvas0Addr);
pr_info("index1: 0x%x, vframe type: 0x%x.\n",
pr_info("\t canvas index1: 0x%x, vframe type: 0x%x.\n",
pos->vf.canvas1Addr, pos->vf.type);
pr_info("\t ratio_control(0x%x).\n", pos->vf.ratio_control);
}
spin_unlock_irqrestore(&p->wt_lock, flags);
pr_info("buffer in temp list:\n");
spin_lock_irqsave(&p->tmp_lock, flags);
list_for_each_entry_safe(pos, tmp, &p->tmp_list, list) {
pr_info("\t index: %u, status %u, canvas index0: 0x%x,",
pr_info("index: %u, status %u, canvas index0: 0x%x,",
pos->vf.index, pos->status, pos->vf.canvas0Addr);
pr_info("index1: 0x%x, vframe type: 0x%x.\n",
pr_info("\t canvas index1: 0x%x, vframe type: 0x%x.\n",
pos->vf.canvas1Addr, pos->vf.type);
pr_info("\t ratio_control(0x%x).\n", pos->vf.ratio_control);
}
spin_unlock_irqrestore(&p->tmp_lock, flags);
pr_info("buffer get count %d.\n", atomic_read(&p->buffer_cnt));
}
/*update the vframe disp_mode
* a.VFRAME_DISP_MODE_UNKNOWN
* b. VFRAME_DISP_MODE_OK
*/
void vdin_vf_disp_mode_update(struct vf_entry *vfe, struct vf_pool *p)
{
unsigned int i;
for (i = p->skip_vf_num; (i > 0) && (i < VFRAME_DISP_MAX_NUM); i--)
p->disp_index[i] = p->disp_index[i - 1];
p->disp_index[0]++;
if (p->disp_index[0] >= VFRAME_DISP_MAX_NUM)
p->disp_index[0] = 0;
vfe->vf.index_disp = p->disp_index[0];
p->disp_mode[p->disp_index[p->skip_vf_num]] = VFRAME_DISP_MODE_OK;
for (i = p->skip_vf_num - 1; (i >= 0) && (i < VFRAME_DISP_MAX_NUM); i--)
p->disp_mode[p->disp_index[i]] = VFRAME_DISP_MODE_UNKNOWN;
}
/*disp mode skip
*skip_vf_num
* 2:last last vframe, 1:last vframe
* 0:current vframe
*/
void vdin_vf_disp_mode_skip(struct vf_pool *p)
{
unsigned int i;
for (i = p->skip_vf_num - 1; (i >= 0) && (i < VFRAME_DISP_MAX_NUM); i--)
p->disp_mode[i] = VFRAME_DISP_MODE_SKIP;
}

53
drivers/amlogic/media/vin/tvin/vdin/vdin_vf.h
View File

@@ -19,13 +19,10 @@
#define __VDIN_VF_H
/* Standard Linux Headers */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/list.h>
/* Amlogic Linux Headers */
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/vfm/vframe_provider.h>
#define VF_LOG_EN
@@ -37,6 +34,16 @@
/* only log backend opertations */
#define VF_LOG_BE
#define VDIN_DV_MAX_NUM 9
#define VF_FLAG_NORMAL_FRAME 0x00000001
#define VF_FLAG_FREEZED_FRAME 0x00000002
#define VFRAME_DISP_MAX_NUM 10
#define VDIN_VF_POOL_FREEZE 0x00000001
#define ISR_LOG_EN
#define VF_LOG_PRINT_MAX_LEN 100
enum vf_operation_e {
VF_OPERATION_INIT = 0,
VF_OPERATION_FPEEK,
@@ -84,9 +91,8 @@ struct vf_log_s {
#endif
#define ISR_LOG_EN
#ifdef ISR_LOG_EN
#define ISR_LOG_LEN 2000
#define ISR_LOG_LEN 2000
struct isr_log_s {
struct timeval isr_time[ISR_LOG_LEN];
unsigned int log_cur;
@@ -94,9 +100,6 @@ struct isr_log_s {
};
#endif
#define VF_FLAG_NORMAL_FRAME 0x00000001
#define VF_FLAG_FREEZED_FRAME 0x00000002
struct vf_entry {
struct vframe_s vf;
@@ -105,28 +108,28 @@ struct vf_entry {
unsigned int flag;
};
#define VDIN_VF_POOL_FREEZE 0x00000001
struct vf_pool {
unsigned int pool_flag;
unsigned int max_size, size;
struct vf_entry *master;
struct vf_entry *slave;
struct list_head wr_list; /* vf_entry */
spinlock_t wr_lock;
unsigned int wr_list_size;
spinlock_t wr_lock;
unsigned int wr_list_size;
struct list_head *wr_next;
struct list_head rd_list; /* vf_entry */
spinlock_t rd_lock;
unsigned int rd_list_size;
spinlock_t rd_lock;
unsigned int rd_list_size;
struct list_head wt_list; /* vframe_s */
spinlock_t wt_lock;
unsigned int fz_list_size;
spinlock_t wt_lock;
unsigned int fz_list_size;
struct list_head fz_list;
spinlock_t fz_lock;
unsigned int tmp_list_size;
spinlock_t fz_lock;
unsigned int tmp_list_size;
struct list_head tmp_list;
spinlock_t tmp_lock;
spinlock_t lock;
spinlock_t log_lock;
spinlock_t dv_lock;/*dolby vision lock*/
#ifdef VF_LOG_EN
struct vf_log_s log;
#endif
@@ -134,7 +137,17 @@ struct vf_pool {
struct isr_log_s isr_log;
#endif
atomic_t buffer_cnt;
unsigned int dv_buf_mem[VDIN_DV_MAX_NUM];
void *dv_buf_vmem[VDIN_DV_MAX_NUM];
unsigned int dv_buf_size[VDIN_DV_MAX_NUM];
char *dv_buf[VDIN_DV_MAX_NUM];
char *dv_buf_ori[VDIN_DV_MAX_NUM];
unsigned int disp_index[VFRAME_DISP_MAX_NUM];
unsigned int skip_vf_num;/*skip pre vframe num*/
enum vframe_disp_mode_e disp_mode[VFRAME_DISP_MAX_NUM];
};
extern unsigned int dolby_size_byte;
extern unsigned int dv_dbg_mask;
extern void vf_log_init(struct vf_pool *p);
extern void vf_log_print(struct vf_pool *p);
@@ -162,6 +175,7 @@ extern struct vf_entry *receiver_vf_peek(struct vf_pool *p);
extern struct vf_entry *receiver_vf_get(struct vf_pool *p);
extern void receiver_vf_put(struct vframe_s *vf, struct vf_pool *p);
extern struct vframe_s *vdin_vf_peek(void *op_arg);
extern struct vframe_s *vdin_vf_get(void *op_arg);
extern void vdin_vf_put(struct vframe_s *vf, void *op_arg);
@@ -171,5 +185,8 @@ extern void vdin_vf_freeze(struct vf_pool *p, unsigned int hold_num);
extern void vdin_vf_unfreeze(struct vf_pool *p);
extern void vdin_dump_vf_state(struct vf_pool *p);
extern void vdin_vf_disp_mode_update(struct vf_entry *vfe, struct vf_pool *p);
extern void vdin_vf_disp_mode_skip(struct vf_pool *p);
#endif /* __VDIN_VF_H */

19
include/linux/amlogic/media/frame_provider/tvin/tvin.h
View File

@@ -330,7 +330,9 @@ enum tvin_sig_fmt_e {
TVIN_SIG_FMT_HDMI_RESERVE11 = 0x44b,
TVIN_SIG_FMT_HDMI_720X480P_60HZ_FRAME_PACKING = 0x44c,
TVIN_SIG_FMT_HDMI_720X576P_50HZ_FRAME_PACKING = 0x44d,
TVIN_SIG_FMT_HDMI_MAX = 0x44e,
TVIN_SIG_FMT_HDMI_640X480P_72HZ = 0x44e,
TVIN_SIG_FMT_HDMI_640X480P_75HZ = 0x44f,
TVIN_SIG_FMT_HDMI_MAX = 0x450,
TVIN_SIG_FMT_HDMI_THRESHOLD = 0x600,
/* Video Formats */
TVIN_SIG_FMT_CVBS_NTSC_M = 0x601,
@@ -340,7 +342,8 @@ enum tvin_sig_fmt_e {
TVIN_SIG_FMT_CVBS_PAL_60 = 0x605,
TVIN_SIG_FMT_CVBS_PAL_CN = 0x606,
TVIN_SIG_FMT_CVBS_SECAM = 0x607,
TVIN_SIG_FMT_CVBS_MAX = 0x608,
TVIN_SIG_FMT_CVBS_NTSC_50 = 0x608,
TVIN_SIG_FMT_CVBS_MAX = 0x609,
TVIN_SIG_FMT_CVBS_THRESHOLD = 0x800,
/* 656 Formats */
TVIN_SIG_FMT_BT656IN_576I_50HZ = 0x801,
@@ -460,7 +463,7 @@ struct tvin_info_s {
enum tvin_sig_status_e status;
enum tvin_color_fmt_e cfmt;
unsigned int fps;
unsigned int reserved;
unsigned int is_dvi;
};
struct tvin_buf_info_s {
@@ -871,6 +874,14 @@ struct tvafe_pin_mux_s {
*adc pll ctl, atv demod & tvafe use the same adc module
* module index: atv demod:0x01; tvafe:0x2
*/
extern void adc_set_pll_cntl(bool on, unsigned int module_sel);
/* extern void adc_set_pll_cntl(bool on, unsigned int module_sel);*/
struct dfe_adcpll_para {
unsigned int adcpllctl;
unsigned int demodctl;
unsigned int atsc;
};
extern int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara);
extern void tvafe_set_ddemod_default(void);/* add for dtv demod*/
#endif

6
include/linux/amlogic/media/frame_provider/tvin/tvin_v4l2.h
View File

@@ -800,9 +800,9 @@ struct vdin_parm_s {
enum bt_path_e bt_path; /* 0:from gpio,1:from csi2 */
unsigned char hsync_phase; /* 1: inverted 0: original */
unsigned char vsync_phase; /* 1: inverted 0: origianl */
unsigned short hs_bp; /* the horizontal start postion of bt656 window */
unsigned short vs_bp; /* the vertical start postion of bt656 window */
unsigned short fid_check_cnt; /* vs check hs timeout cnt */
unsigned short hs_bp;/* the horizontal start postion of bt656 window */
unsigned short vs_bp;/* the vertical start postion of bt656 window */
unsigned short fid_check_cnt; /* vs check hs timeout cnt */
/*for isp tell different frontends such as bt656/mipi */
enum tvin_port_e isp_fe_port;
/*for vdin cfmt convert & scale&skip */

1
include/linux/amlogic/media/vfm/vframe_provider.h
View File

@@ -49,6 +49,7 @@ struct provider_aux_req_s {
char *aux_buf;
int aux_size;
int dv_enhance_exist;
int low_latency;
};
struct provider_disp_mode_req_s {
/*input*/