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arm64: dts: rockchip: rk3588s add sdmmc and sdio node

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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iac1fe3671d241c0ca2581f01b3e3861dbcac3693
This commit is contained in:
Shawn Lin
2021-08-24 14:50:30 +08:00
committed by Tao Huang
parent eeccdd466a
commit 75d88fe4bb
1 changed files with 20 additions and 4 deletions
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24
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -418,16 +418,29 @@
status = "disabled";
};
sdmmc0: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc",
"rockchip,rk3288-dw-mshc";
sdmmc: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <150000000>;
clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
status = "disabled";
};
sdio: mmc@fe2d0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2d0000 0x0 0x4000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
status = "disabled";
};
@@ -435,10 +448,13 @@
compatible = "rk3588,dwcmshc-sdhci", "rockchip,dwcmshc-sdhci";
reg = <0x0 0xfe2e0000 0x0 0x10000>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>;
assigned-clock-rates = <200000000>, <24000000>;
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
<&cru TMCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
max-frequency = <200000000>;
status = "disabled";
};