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arm64: dts: rockchip: rk3568: Fix all wrong RID and MSI(-x) mappings

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For hierarchy root complexes under same PCIe domain:

		domain N
	root bridge bus(BDF: 00:00.0)
--------------------------------------------
 RC1(01:00.0)	RC2(N+1:00.0)	RC3(N+N+1:00.0)
 |		 |		 |
---             ---             ---
...		...		...

Dev1(last N)   Dev2(last M)     Dev3

They can assign all bus ranges from zero, and the bridge
will scan RCs and take over all the bus assign from top on.
So the the unique requester ID(namely bdf) will be assigned
to each device.

But for seperate RCs without root bridge bus, we should
carefully assigne bus ranges for MSI(-x) mappings. MSI
controller should be in the following format:

msi-map = < rid-base, //first RID matched by the entry
	    msi-controller,
	    msi-base, //msi-specifier 1st RID matched entry
	    length>   //how many consecutive RIDs are matched

rid-base is formated as 1 byte of bus + 1 byte of dev and
function number. And it's the same for filter of mapping
for msi-base.

For this platform:

domain 0 --RC1(00:00.0) --- Dev1(01:00.0) |
			--- Dev2(02:00.0) |____ 0x0 ~ 0xf
			....		  |
			--- DevN(0f:00.0) |

For reguster ID(BDF) under this RC, we should assigne
RID base from 0x0. Length is 16 buses, name 0x10, and
the lower bytes is 0x00 for DF. So all the RID is 0x0000.
Also the RID base should be equal to out-base.

For PCIe2x1, we limit buses from 0x0 to 0xf, ID mapping
looks like:

msi-map = <0x0000 &its 0x0000 0x1000>;
           RID        out-base length

Any BDF under PCIe2x1 was allocated and hit the mapping vects
and entry between 0x0000 and 0x0000 + 0x1000.

domain 1 --RC2(10:00.0) --- Dev1(11:00.0) |
			--- Dev2(12:00.0) |____ 0x10 ~ 0x1f
			....		  |
			--- DevN(1f:00.0) |

For reguster ID(BDF) under this RC, we should assigne
RID base from 0x1000. Length is 16 buses, namely 0x10, and
the lower byte is 0x00 for DF. So all the RID is 0x1000.
Also the RID base should be equal to out-base.

For PCIe3x1, we limit buses from 0x10 to 0x1f, ID mapping
looks like:

msi-map = <0x1000 &its 0x1000 0x1000>;
           RID        out-base length

Any BDF under PCIe3x1 was allocated and hit the mapping vects
and entry between 0x1000 and 0x1000 + 0x1000.

domain 2 --RC3(20:00.0) --- Dev1(21:00.0) |
			--- Dev2(22:00.0) |____ 0x20 ~ 0x2f
			....		  |
			--- DevN(2f:00.0) |

For reguster ID(BDF) under this RC, we should assigne
RID base from 0x2000. Length is 16 buses, name 0x10, and
the lower bytes is 0x00 for DF. So all the RID is 0x2000.
Also the RID base should be equal to out-base.

For PCIe3x2, we limit buses from 0x20 to 0x2f, ID mapping
looks like:

msi-map = <0x2000 &its 0x2000 0x1000>;
           RID        out-base length

Any BDF under PCIe3x2 was allocated and hit the mapping vects
and entry between 0x2000 and 0x2000 + 0x1000.

Change-Id: I1fe9f2a6e89fd9a4c055f0a0177be2b38cc10dc6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2020-12-01 14:08:15 +08:00
parent e658b2131e
commit 7620167fdb
1 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -362,6 +362,7 @@
its: interrupt-controller@fd440000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xfd440000 0x0 0x20000>;
status = "disabled";
};
@@ -1679,7 +1680,7 @@
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x1f>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
<&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>;
clock-names = "aclk_mst", "aclk_slv",
@@ -1715,7 +1716,7 @@
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x1f>;
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>;
clock-names = "aclk_mst", "aclk_slv",
@@ -1731,7 +1732,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x0 &its 0x3000 0x1000>;
msi-map = <0x1000 &its 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -1752,7 +1753,7 @@
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x1f>;
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>;
clock-names = "aclk_mst", "aclk_slv",
@@ -1768,7 +1769,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x0 &its 0x2000 0x1000>;
msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";