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clk: rockchip: rk3366: pll's rate support 480MHz 520MHz 576MHz 750Mhz

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Change-Id: I56c75018ffd27a21ac87c2004eb5bd6a3b1e0e3d
Signed-off-by: Feng Xiao <xf@rock-chips.com>
This commit is contained in:
Feng Xiao
2016-03-02 23:04:33 +08:00
parent 07aae424ae
commit 764276eeef
1 changed files with 4 additions and 0 deletions
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4
drivers/clk/rockchip/clk-rk3366.c
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@@ -60,12 +60,16 @@ static struct rockchip_pll_rate_table rk3366_pll_rates[] = {
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE( 750000000, 2, 125, 2, 1, 1, 0),
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE( 576000000, 1, 96, 4, 1, 1, 0),
RK3036_PLL_RATE( 520000000, 1, 65, 3, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 480000000, 1, 80, 4, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),