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arm64: dts: rockchip: rk3562: modify the default drive strength of lcdc pins

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According to the SI report, set default drive strength
as below:

clk      level_4
den      level_3
hsync    level_3
data0-23 level_3

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ie14bb84e485c87a6f153bf0b23e13adeb21dadca
This commit is contained in:
Damon Ding
2023-07-15 15:42:39 +08:00
committed by Tao Huang
parent e2852b6423
commit 764c782d27
1 changed files with 103 additions and 103 deletions
Download Patch File Download Diff File Expand all files Collapse all files

206
arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
View File

@@ -2071,61 +2071,61 @@
vo_pins: vo-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d0 */
<4 RK_PA4 1 &pcfg_pull_none>,
<4 RK_PA4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d1 */
<4 RK_PA5 1 &pcfg_pull_none>,
<4 RK_PA5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d2 */
<4 RK_PB2 1 &pcfg_pull_none>,
<4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d8 */
<4 RK_PA6 1 &pcfg_pull_none>,
<4 RK_PA6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d9 */
<4 RK_PA7 1 &pcfg_pull_none>,
<4 RK_PA7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d16 */
<4 RK_PB0 1 &pcfg_pull_none>,
<4 RK_PB0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d17 */
<4 RK_PB1 1 &pcfg_pull_none>,
<4 RK_PB1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d18 */
<4 RK_PB3 1 &pcfg_pull_none>,
<4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
};
};
@@ -2178,175 +2178,175 @@
bt656_pins: bt656-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>;
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb3x8_pins_m0: rgb3x8-pins-m0 {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb3x8_pins_m1: rgb3x8-pins-m1 {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb565_pins: rgb565-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb666_pins: rgb666-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d2 */
<4 RK_PB2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d18 */
<4 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
};
};