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UPSTREAM: clk: rockchip: fix rk3399 aclk_vio gate bit

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Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10.

Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit a3f457d963)

Change-Id: I6e962f61a7f918e7945ac93dca6a039e90a0df3c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Chris Zhong
2016-08-09 11:02:33 -07:00
committed by Tao Huang
parent 5e64ddee62
commit 7738401fb0
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3399.c
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@@ -1166,8 +1166,8 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
/* vio */
COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 10, GFLAGS),
COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(11), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 1, GFLAGS),