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arm64: dts: rockchip: rk3588: Add dphy node

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Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I0d5796c64a723a27a7b92e07e16dbac1863849ad
This commit is contained in:
Zefa Chen
2021-11-03 20:54:09 +08:00
committed by Tao Huang
parent 4dbc12fe3d
commit 7844ec4b7b
2 changed files with 81 additions and 0 deletions
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36
arch/arm64/boot/dts/rockchip/rk3588.dtsi
View File

@@ -8,6 +8,9 @@
/ {
aliases {
csi2dphy3 = &csi2_dphy3;
csi2dphy4 = &csi2_dphy4;
csi2dphy5 = &csi2_dphy5;
dp0 = &dp0;
dp1 = &dp1;
edp0 = &edp0;
@@ -21,6 +24,27 @@
rkcif_mipi_lvds5= &rkcif_mipi_lvds5;
};
/* dphy1 full mode */
csi2_dphy3: csi2-dphy3 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy1 split mode 01 */
csi2_dphy4: csi2-dphy4 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy1 split mode 23 */
csi2_dphy5: csi2-dphy5 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy1_hw>;
status = "disabled";
};
rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
compatible = "rockchip,rkcif-mipi-lvds";
rockchip,hw = <&rkcif>;
@@ -675,6 +699,18 @@
};
};
csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 {
compatible = "rockchip,rk3588-csi2-dphy-hw";
reg = <0x0 0xfedc8000 0x0 0x8000>;
clocks = <&cru PCLK_CSIPHY1>;
clock-names = "pclk";
resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>;
reset-names = "srst_csiphy1", "srst_p_csiphy1";
rockchip,grf = <&mipidphy1_grf>;
rockchip,sys_grf = <&sys_grf>;
status = "disabled";
};
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;

45
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -20,6 +20,9 @@
aliases {
csi2dcphy0 = &csi2_dcphy0;
csi2dcphy1 = &csi2_dcphy1;
csi2dphy0 = &csi2_dphy0;
csi2dphy1 = &csi2_dphy1;
csi2dphy2 = &csi2_dphy2;
dsi0 = &dsi0;
dsi1 = &dsi1;
ethernet1 = &gmac1;
@@ -281,6 +284,26 @@
csi2_dcphy1: csi2-dcphy1 {
compatible = "rockchip,rk3588-csi2-dcphy";
rockchip,hw = <&csi2_dcphy1_hw>;
};
/* dphy0 full mode */
csi2_dphy0: csi2-dphy0 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy0_hw>;
status = "disabled";
};
/* dphy0 split mode 01 */
csi2_dphy1: csi2-dphy1 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy0_hw>;
status = "disabled";
};
/* dphy0 split mode 23 */
csi2_dphy2: csi2-dphy2 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy0_hw>;
status = "disabled";
};
@@ -744,6 +767,16 @@
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
mipidphy0_grf: syscon@fd5b4000 {
compatible = "rockchip,mipi-dphy-grf", "syscon";
reg = <0x0 0xfd5b4000 0x0 0x1000>;
};
mipidphy1_grf: syscon@fd5b5000 {
compatible = "rockchip,mipi-dphy-grf", "syscon";
reg = <0x0 0xfd5b5000 0x0 0x1000>;
};
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfd5bc000 0x0 0x100>;
@@ -3874,6 +3907,18 @@
status = "disabled";
};
csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 {
compatible = "rockchip,rk3588-csi2-dphy-hw";
reg = <0x0 0xfedc0000 0x0 0x8000>;
clocks = <&cru PCLK_CSIPHY0>;
clock-names = "pclk";
resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>;
reset-names = "srst_csiphy0", "srst_p_csiphy0";
rockchip,grf = <&mipidphy0_grf>;
rockchip,sys_grf = <&sys_grf>;
status = "disabled";
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;