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clk: rockchip: rk3066a: Rename i2s hclk id

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Change-Id: I0a5ccf1846950353ea6fc6980c1c4a4fb3457fd1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2017-12-06 17:53:00 +08:00
committed by Tao Huang
parent b1e59714a2
commit 79747ecfb6
4 changed files with 10 additions and 10 deletions
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6
arch/arm/boot/dts/rk3066a.dtsi
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@@ -235,7 +235,7 @@
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <2>;
status = "disabled";
@@ -252,7 +252,7 @@
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S1>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "disabled";
@@ -269,7 +269,7 @@
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
clocks = <&cru HCLK_I2S1_2CH>, <&cru SCLK_I2S2>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "disabled";

2
arch/arm/boot/dts/rk3188.dtsi
View File

@@ -96,7 +96,7 @@
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "disabled";

6
drivers/clk/rockchip/clk-rk3188.c
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@@ -461,7 +461,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
/* hclk_ahb2apb is part of a clk branch */
@@ -646,8 +646,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(0), 12, GFLAGS,
&rk3066a_i2s2_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),

6
include/dt-bindings/clock/rk3188-cru-common.h
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@@ -122,9 +122,9 @@
#define HCLK_OTG0 451
#define HCLK_EMAC 452
#define HCLK_SPDIF 453
#define HCLK_I2S0 454
#define HCLK_I2S1 455
#define HCLK_I2S2 456
#define HCLK_I2S0_2CH 454
#define HCLK_I2S1_2CH 455
#define HCLK_I2S_8CH 456
#define HCLK_OTG1 457
#define HCLK_HSIC 458
#define HCLK_HSADC 459