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arm64: tegra: Update SDMMC1/3 clock source for Tegra194

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The default parent for SDMMC1/3 clock sources can provide maximum frequency
of 136MHz for SDR104 mode.
Update parent clock source for SDMMC1/SDMMC3 instances
to increase the output clock frequency to 195MHz and improve the perf.

Signed-off-by: Aniruddha Rao <anrao@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Aniruddha Rao
2022-03-16 15:14:45 +05:30
committed by Thierry Reding
parent 3123109284
commit 7ac853ba78
1 changed files with 10 additions and 0 deletions
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10
arch/arm64/boot/dts/nvidia/tegra194.dtsi
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@@ -934,6 +934,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
<&bpmp TEGRA194_CLK_PLLC4_MUXED>;
assigned-clock-parents =
<&bpmp TEGRA194_CLK_PLLC4_MUXED>,
<&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -968,6 +973,11 @@
clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
<&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
<&bpmp TEGRA194_CLK_PLLC4_MUXED>;
assigned-clock-parents =
<&bpmp TEGRA194_CLK_PLLC4_MUXED>,
<&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,