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iio: adc: at91-sama5d2_adc: fix differential channels in triggered mode
commita500f3bd78upstream. The differential channels require writing the channel offset register (COR). Otherwise they do not work in differential mode. The configuration of COR is missing in triggered mode. Fixes:5e1a1da0f8("iio: adc: at91-sama5d2_adc: add hw trigger and buffer support") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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committed by
Greg Kroah-Hartman
parent
4d71a4f761
commit
7ad22950ca
@@ -723,6 +723,7 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
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for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
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struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
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u32 cor;
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if (!chan)
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continue;
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@@ -731,6 +732,20 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
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chan->type == IIO_PRESSURE)
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continue;
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if (state) {
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cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
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if (chan->differential)
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cor |= (BIT(chan->channel) |
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BIT(chan->channel2)) <<
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AT91_SAMA5D2_COR_DIFF_OFFSET;
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else
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cor &= ~(BIT(chan->channel) <<
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AT91_SAMA5D2_COR_DIFF_OFFSET);
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at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
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}
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if (state) {
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at91_adc_writel(st, AT91_SAMA5D2_CHER,
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BIT(chan->channel));
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