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pinctrl: rockchip: sync difference with upstream version

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Some difference made during driver upstream review, this patch sync the
driver with upstream version.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I0da05d04f54bfc8e83afa28692c658b0b4d2604b
This commit is contained in:
Jianqun Xu
2021-12-01 14:34:38 +08:00
committed by Tao Huang
parent 0d7bc5495a
commit 7bb2c21642
2 changed files with 67 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/pinctrl/pinctrl-rockchip.c
View File

@@ -20,10 +20,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
@@ -2967,13 +2967,13 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
return rc;
break;
case PIN_CONFIG_OUTPUT:
rc = rockchip_get_mux(bank, pin - bank->pin_base);
if (rc != 0) {
dev_err(info->dev, "pin-%d has been mux to func%d\n", pin, rc);
rc = rockchip_set_mux(bank, pin - bank->pin_base,
RK_FUNC_GPIO);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
}
rc = gpio->direction_output(gpio, pin - bank->pin_base, arg);
rc = gpio->direction_output(gpio, pin - bank->pin_base,
arg);
if (rc)
return rc;
break;
@@ -3045,9 +3045,12 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_OUTPUT:
rc = rockchip_get_mux(bank, pin - bank->pin_base);
if (rc != 0) {
dev_err(info->dev, "pin-%d has been mux to func%d\n", pin, rc);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
if (!gpio || !gpio->get) {
arg = 0;
break;
}
rc = gpio->get(gpio, pin - bank->pin_base);

91
drivers/pinctrl/pinctrl-rockchip.h
View File

@@ -1,6 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* With some ideas taken from pinctrl-samsung:
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* https://www.linaro.org
*
* and pinctrl-at91:
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*/
#ifndef _PINCTRL_ROCKCHIP_H
@@ -188,6 +200,24 @@ enum rockchip_pinctrl_type {
RK3588,
};
/**
* struct rockchip_gpio_regs
* @port_dr: data register
* @port_ddr: data direction register
* @int_en: interrupt enable
* @int_mask: interrupt mask
* @int_type: interrupt trigger type, such as high, low, edge trriger type.
* @int_polarity: interrupt polarity enable register
* @int_bothedge: interrupt bothedge enable register
* @int_status: interrupt status register
* @int_rawstatus: int_status = int_rawstatus & int_mask
* @debounce: enable debounce for interrupt signal
* @dbclk_div_en: enable divider for debounce clock
* @dbclk_div_con: setting for divider of debounce clock
* @port_eoi: end of interrupt of the port
* @ext_port: port data from external
* @version_id: controller version register
*/
struct rockchip_gpio_regs {
u32 port_dr;
u32 port_ddr;
@@ -207,6 +237,7 @@ struct rockchip_gpio_regs {
};
/**
* struct rockchip_iomux
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
@@ -217,7 +248,7 @@ struct rockchip_iomux {
int offset;
};
/**
/*
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
enum rockchip_pin_drv_type {
@@ -229,7 +260,7 @@ enum rockchip_pin_drv_type {
DRV_TYPE_MAX
};
/**
/*
* enum type index corresponding to rockchip_pull_list arrays index.
*/
enum rockchip_pin_pull_type {
@@ -239,27 +270,7 @@ enum rockchip_pin_pull_type {
};
/**
* enum mux route register type, should be invalid/default/topgrf/pmugrf.
* INVALID: means do not need to set mux route
* DEFAULT: means same regmap as pin iomux
* TOPGRF: means mux route setting in topgrf
* PMUGRF: means mux route setting in pmugrf
*/
enum rockchip_pin_route_type {
ROUTE_TYPE_DEFAULT = 0,
ROUTE_TYPE_TOPGRF = 1,
ROUTE_TYPE_PMUGRF = 2,
ROUTE_TYPE_INVALID = -1,
};
enum rockchip_mux_route_location {
ROCKCHIP_ROUTE_SAME = 0,
ROCKCHIP_ROUTE_PMU,
ROCKCHIP_ROUTE_GRF,
};
/**
* struct rockchip_drv
* @drv_type: drive strength variant using rockchip_perpin_drv_type
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
@@ -273,9 +284,10 @@ struct rockchip_drv {
};
/**
* @dev: device of the gpio bank
* struct rockchip_pin_bank
* @dev: the pinctrl device bind to the bank
* @reg_base: register base of the gpio bank
* @reg_pull: optional separate register for additional pull settings
* @regmap_pull: optional separate register for additional pull settings
* @clk: clock of the gpio bank
* @db_clk: clock of the gpio debounce
* @irq: interrupt of the gpio bank
@@ -287,17 +299,19 @@ struct rockchip_drv {
* @iomux: array describing the 4 iomux sources of the bank
* @drv: array describing the 4 drive strength sources of the bank
* @pull_type: array describing the 4 pull type sources of the bank
* @valid: is all necessary information present
* @of_node: dt node of this bank
* @drvdata: common pinctrl basedata
* @domain: irqdomain of the gpio bank
* @gpio_chip: gpiolib chip
* @grange: gpio range
* @slock: spinlock for the gpio bank
* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
* @recalced_mask: bit mask to indicate a need to recalulate the mask
* @route_mask: bits describing the routing pins of per bank
*/
struct rockchip_pin_bank {
struct device *dev;
struct device *dev;
void __iomem *reg_base;
struct regmap *regmap_pull;
struct clk *clk;
@@ -311,6 +325,7 @@ struct rockchip_pin_bank {
struct rockchip_iomux iomux[4];
struct rockchip_drv drv[4];
enum rockchip_pin_pull_type pull_type[4];
bool valid;
struct device_node *of_node;
struct rockchip_pinctrl *drvdata;
struct irq_domain *domain;
@@ -340,6 +355,12 @@ struct rockchip_mux_recalced_data {
u8 mask;
};
enum rockchip_mux_route_location {
ROCKCHIP_ROUTE_SAME = 0,
ROCKCHIP_ROUTE_PMU,
ROCKCHIP_ROUTE_GRF,
};
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @bank_num: bank number.
@@ -378,11 +399,11 @@ struct rockchip_pin_ctrl {
int (*soc_data_init)(struct rockchip_pinctrl *info);
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
@@ -402,9 +423,7 @@ struct rockchip_pin_config {
* @name: name of the pin group, used to lookup the group.
* @pins: the pins included in this group.
* @npins: number of pins included in this group.
* @func: the mux function number to be programmed when selected.
* @configs: the config values to be set for each pin
* @nconfigs: number of configs for each pin
* @data: local pin configuration
*/
struct rockchip_pin_group {
const char *name;
@@ -417,7 +436,7 @@ struct rockchip_pin_group {
* struct rockchip_pmx_func: represent a pin function.
* @name: name of the pin function, used to lookup the function.
* @groups: one or more names of pin groups that provide this function.
* @num_groups: number of groups included in @groups.
* @ngroups: number of groups included in @groups.
*/
struct rockchip_pmx_func {
const char *name;