shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-09 04:10:18 +09:00
Code Issues Packages Projects Releases Wiki Activity

video/rockchip: rga2: Fixup warning "-Wmissing-prototypes"

Browse Source 
Change-Id: I504d8615a8dae1f3b348c11ee1c0018d9c4d4e41
Signed-off-by: Putin Lee <putin.li@rock-chips.com>
This commit is contained in:
Putin Lee
2018-05-09 10:24:44 +08:00
committed by Tao Huang
parent 11094e35c3
commit 7c1beeafdf
2 changed files with 17 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/video/rockchip/rga2/rga2_drv.c
View File

@@ -1228,7 +1228,7 @@ static long compat_rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
#endif
long rga2_ioctl_kernel(struct rga_req *req_rga)
static long rga2_ioctl_kernel(struct rga_req *req_rga)
{
int ret = 0;
rga2_session *session;

49
drivers/video/rockchip/rga2/rga2_reg_info.c
View File

@@ -37,8 +37,7 @@
extern unsigned int rga2_ROP3_code[256];
void
RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
{
RK_U32 *bRGA_SRC_INFO;
RK_U32 *bRGA_SRC_X_FACTOR;
@@ -126,8 +125,7 @@ RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
reg = ((reg & (~m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE)) | (s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(y_flag)));
}
void
RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_MODE_CTL;
RK_U32 reg = 0;
@@ -150,8 +148,7 @@ RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
*bRGA_MODE_CTL = reg;
}
void
RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
static void RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_SRC_INFO;
RK_U32 *bRGA_SRC_BASE0, *bRGA_SRC_BASE1, *bRGA_SRC_BASE2;
@@ -313,9 +310,7 @@ RGA2_set_reg_src_info(RK_U8 *base, struct rga2_req *msg)
*bRGA_SRC_TR_COLOR1 = msg->color_key_max;
}
void
RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_DST_INFO;
RK_U32 *bRGA_DST_BASE0, *bRGA_DST_BASE1, *bRGA_DST_BASE2, *bRGA_SRC_BASE3;
@@ -570,8 +565,7 @@ RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
*bRGA_SRC_BASE3 = (RK_U32)s_y_lt_addr;
}
void
RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)
static void RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_ALPHA_CTRL0;
RK_U32 *bRGA_ALPHA_CTRL1;
@@ -618,8 +612,7 @@ RGA2_set_reg_alpha_info(u8 *base, struct rga2_req *msg)
}
}
void
RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
static void RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_ALPHA_CTRL0;
RK_U32 *bRGA_ROP_CTRL0;
@@ -659,10 +652,7 @@ RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
}
void
RGA2_set_reg_color_palette(RK_U8 *base, struct rga2_req *msg)
static void RGA2_set_reg_color_palette(RK_U8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_SRC_BASE0, *bRGA_SRC_INFO, *bRGA_SRC_VIR_INFO, *bRGA_SRC_ACT_INFO, *bRGA_SRC_FG_COLOR, *bRGA_SRC_BG_COLOR;
RK_U32 *p;
@@ -721,8 +711,7 @@ RGA2_set_reg_color_palette(RK_U8 *base, struct rga2_req *msg)
}
void
RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)
static void RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_CF_GR_A;
RK_U32 *bRGA_CF_GR_B;
@@ -769,9 +758,7 @@ RGA2_set_reg_color_fill(u8 *base, struct rga2_req *msg)
*bRGA_SRC_VIR_INFO = mask_stride << 16;
}
void
RGA2_set_reg_update_palette_table(RK_U8 *base, struct rga2_req *msg)
static void RGA2_set_reg_update_palette_table(RK_U8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_MASK_BASE;
RK_U32 *bRGA_FADING_CTRL;
@@ -784,8 +771,7 @@ RGA2_set_reg_update_palette_table(RK_U8 *base, struct rga2_req *msg)
}
void
RGA2_set_reg_update_patten_buff(RK_U8 *base, struct rga2_req *msg)
static void RGA2_set_reg_update_patten_buff(RK_U8 *base, struct rga2_req *msg)
{
u32 *bRGA_PAT_MST;
u32 *bRGA_PAT_CON;
@@ -816,9 +802,7 @@ RGA2_set_reg_update_patten_buff(RK_U8 *base, struct rga2_req *msg)
*bRGA_FADING_CTRL = (num << 8) | offset;
}
void
RGA2_set_pat_info(RK_U8 *base, struct rga2_req *msg)
static void RGA2_set_pat_info(RK_U8 *base, struct rga2_req *msg)
{
u32 *bRGA_PAT_CON;
u32 *bRGA_FADING_CTRL;
@@ -841,9 +825,7 @@ RGA2_set_pat_info(RK_U8 *base, struct rga2_req *msg)
*bRGA_FADING_CTRL = (num << 8) | offset;
}
void
RGA2_set_mmu_info(RK_U8 *base, struct rga2_req *msg)
static void RGA2_set_mmu_info(RK_U8 *base, struct rga2_req *msg)
{
RK_U32 *bRGA_MMU_CTRL1;
RK_U32 *bRGA_MMU_SRC_BASE;
@@ -913,7 +895,7 @@ RGA2_gen_reg_info(RK_U8 *base , struct rga2_req *msg)
}
void format_name_convert(uint32_t *df, uint32_t sf)
static void format_name_convert(uint32_t *df, uint32_t sf)
{
/*
RK_FORMAT_RGBA_8888 = 0x0,
@@ -1185,7 +1167,7 @@ void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
}
}
void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src)
static void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src)
{
dst->yrgb_addr = src->yrgb_addr; /* yrgb mem addr */
dst->uv_addr = src->uv_addr; /* cb/cr mem addr */
@@ -1201,7 +1183,8 @@ void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src)
dst->vir_h = src->vir_h;
dst->endian_mode = src->endian_mode; //for BPP
dst->alpha_swap = src->alpha_swap;
}
}
void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)
{
u16 alpha_mode_0, alpha_mode_1;