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ARM: dts: rockchip: Add mmc for rk3506g-iotest

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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I2e01d243f475642a53cd73a99b0b47c1b8290613
This commit is contained in:
Shawn Lin
2024-06-29 08:52:27 +08:00
committed by Tao Huang
parent 8b5191780e
commit 7c31bea0de
1 changed files with 68 additions and 0 deletions
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68
arch/arm/boot/dts/rk3506g-iotest-v10.dts
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@@ -53,6 +53,28 @@
vin-supply = <&vcc_sys>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
vccio_sd: vccio-sd {
compatible = "regulator-gpio";
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
states = <3300000 1
1800000 0>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_volt>;
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
@@ -110,6 +132,52 @@
};
};
&mmc {
/* For SDMMC */
no-sdio;
no-mmc;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins &sdmmc_det>;
vqmmc-supply = <&vccio_sd>;
vmmc-supply = <&vcc3v3_sd>;
/* For eMMC
* no-sdio;
* no-sd;
* cap-mmc-highspeed;
* cap-sd-highspeed;
* non-removable;
* mmc-hs200-1_8v;
* pinctrl-names = "default";
* pinctrl-0 = <&sdmmc_clk_pins &sdmmc_cmd_pins &sdmmc_bus4_pins>;
* vqmmc-supply = <&vccio_sd>;
* vmmc-supply = <&vcc3v3_sd>;
*/
status = "okay";
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
/omit-if-no-ref/
sdmmc_volt: sdmmc-volt {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
/omit-if-no-ref/
sdmmc_det: sdmmc-det {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm0_4ch_0 {
pinctrl-names = "active";
pinctrl-0 = <&rm_io21_pwm0_ch0>;