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USB: set usbphy_480m clk rate 480MHz.

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This commit is contained in:
wlf
2014-04-17 17:58:59 +08:00
parent e544f6840d
commit 7c4667f203
4 changed files with 14 additions and 3 deletions
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6
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -1049,8 +1049,10 @@
compatible = "rockchip,rk3288_usb20_host";
reg = <0xff540000 0x40000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates13 6>, <&clk_gates7 7>;
clock-names = "clk_usbphy1", "hclk_usb1";
clocks = <&clk_gates13 6>, <&clk_gates7 7>,
<&usbphy_480m>;
clock-names = "clk_usbphy1", "hclk_usb1",
"usbphy_480m";
};
usb2: usb@ff500000 {

1
drivers/usb/dwc_otg_310/dwc_otg_driver.c
View File

@@ -1141,6 +1141,7 @@ static int host20_driver_probe(struct platform_device *_dev)
goto fail;
}
clk_set_rate(pldata->phyclk_480m, 480000000);
/*
* Enable the global interrupt after all the interrupt
* handlers are installed if there is no ADP support else

1
drivers/usb/dwc_otg_310/usbdev_rk.h
View File

@@ -57,6 +57,7 @@ struct dwc_otg_platform_data {
struct clk* phyclk;
struct clk* ahbclk;
struct clk* busclk;
struct clk* phyclk_480m;
int phy_status;
void (*hw_init)(void);
void (*phy_suspend)(void* pdata, int suspend);

9
drivers/usb/dwc_otg_310/usbdev_rk32.c
View File

@@ -215,7 +215,7 @@ static void usb20host_soft_reset(void)
static void usb20host_clock_init(void* pdata)
{
struct dwc_otg_platform_data *usbpdata=pdata;
struct clk* ahbclk,*phyclk;
struct clk* ahbclk, *phyclk, *phyclk_480m;
ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb1");
if (IS_ERR(ahbclk)) {
@@ -229,8 +229,15 @@ static void usb20host_clock_init(void* pdata)
return;
}
phyclk_480m = devm_clk_get(usbpdata->dev, "usbphy_480m");
if (IS_ERR(phyclk_480m)) {
dev_err(usbpdata->dev, "Failed to get usbphy_480m\n");
return;
}
usbpdata->phyclk = phyclk;
usbpdata->ahbclk = ahbclk;
usbpdata->phyclk_480m = phyclk_480m;
}
static void usb20host_clock_enable(void* pdata, int enable)