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fixed : ft test config

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xxx
2014-06-27 18:23:08 +08:00
parent e4d2240463
commit 7c4ae262d3
3 changed files with 62 additions and 56 deletions
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10
arch/arm/boot/dts/rk3288-ft.dts
View File

@@ -16,16 +16,18 @@
status = "okay";
};
rockchip_ft_test {
// rockchip,arm_rate =<408000000 504000000 600000000 792000000>;
// firs rate is setting in rockchip_clocks_init,so it is set 0xfffffffff
rockchip_ft_test {
// firs rate is setting in rockchip_clocks_init,so it is set 0xfffffffff
//rockchip,arm_rate =<0xffffffff 456000000 504000000 552000000>;
rockchip,arm_rate =<0xffffffff (1728000000*1) (1752000000*1) (1800000000*1)>;
rockchip,l1_tst_cnt=<(5*10*2-10) (5*10*2-10) (5*10*2-10) (80-10+0) >;
rockchip,l2_cpy_cnt= <5 5 4 (4+0)>;
rockchip,ftt_tst_cnt= <1 1 1 (0+0)>;
rockchip,pi_tst_cnt= <12 12 10 (8+0)>;
rockchip,stp_task_num= <300 250 250 (80+0)>;
rockchip,ft_end_cnt= <0x23>;
rockchip,ft_end_cnt= <(0x24)>;
//ready_pin idle_pin
rockchip,ft_vol_gpios= <GPIO0_C2 GPIO0_A0>;
};
};

11
arch/arm/configs/rockchip_ft_defconfig
View File

@@ -23,10 +23,6 @@ CONFIG_RK_FT_TEST=y
# CONFIG_ARM_THUMB is not set
# CONFIG_SWP_EMULATE is not set
# CONFIG_KUSER_HELPERS is not set
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_SMP=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
@@ -61,6 +57,13 @@ CONFIG_SRAM=y
# CONFIG_HWMON is not set
# CONFIG_IEP is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_STAGING=y
CONFIG_ANDROID=y
# CONFIG_ANDROID_TIMED_OUTPUT is not set
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set

97
arch/arm/mach-rockchip/rk_pm_tests/ft/ft_test.c Normal file → Executable file
View File

@@ -99,7 +99,7 @@ const static unsigned int ftt_tst_cnt [TST_SETUPS]={1,1,1,0};
const static unsigned int pi_tst_cnt[TST_SETUPS]={12,12,10,8};
const static unsigned int stp_task_num[TST_SETUPS]={300,250,250,80};
static u32 ft_end_cnt=0x24;
static u32 ft_end_cnt=0x20;
//
#define get_setup_tasks(a) ft_get_min(a,TST_TASK_NUM)
@@ -616,25 +616,20 @@ int ft_cpu_test_type0_check(int steps,const char *str)
return ret;
}
/*************************************type1 rate tst case**************************************/
#define ENABLE_FT_TEST_GPIO // for ft seting 1.6G volt
#ifdef ENABLE_FT_TEST_GPIO
static u32 ft_client_ready_pin =0;
static u32 ft_client_idle_pin =0;
#define FT_CLIENT_READY_PIN (0x0c20)
#define FT_CLIENT_IDLE_PIN (0x0a00)
#include "rk_ft_io.c"
#endif
//uint32_t ddr_change_freq(uint32_t nMHz);
//#define FT_CLIENT_READY_PIN (0x0c20)
//#define FT_CLIENT_IDLE_PIN (0x0a00)
int ft_cpu_test_type1_check(int steps,const char *str)
{
int cpu, ret = 0,i;
int rate;
#ifdef ENABLE_FT_TEST_GPIO
u8 idle_gpio_level;
#endif
if(arm_setups_rate[steps])
{
@@ -656,24 +651,20 @@ int ft_cpu_test_type1_check(int steps,const char *str)
#endif
}
if(ft_client_ready_pin&&ft_client_ready_pin)
{
#ifdef ENABLE_FT_TEST_GPIO
//ft_printk("S%s,will set gpio\n",str);
idle_gpio_level=gpio_get_input_level(FT_CLIENT_IDLE_PIN);
// send msg to ctr board to up the volt
gpio_set_output_level(FT_CLIENT_READY_PIN,RKPM_GPIO_OUT_H);
// waiting for volt upping ok
while( idle_gpio_level== gpio_get_input_level(FT_CLIENT_IDLE_PIN));
gpio_set_output_level(FT_CLIENT_READY_PIN,RKPM_GPIO_OUT_L);
//ft_printk("S%s,set gpio end\n",str);
#endif
//ft_printk("S%s,will set gpio\n",str);
idle_gpio_level=gpio_get_input_level(ft_client_idle_pin);
// send msg to ctr board to up the volt
gpio_set_output_level(ft_client_ready_pin,RKPM_GPIO_OUT_H);
// waiting for volt upping ok
while( idle_gpio_level== gpio_get_input_level(ft_client_idle_pin));
gpio_set_output_level(ft_client_ready_pin,RKPM_GPIO_OUT_L);
//ft_printk("S%s,set gpio end\n",str);
}
if(arm_setups_rate[steps]>=rate)
{
clk_set_rate(arm_clk,arm_setups_rate[steps]);
@@ -918,9 +909,9 @@ int rk_ft_tests_cpus_init(int cpu)
static int __init rk_ft_tests_init(void)
{
int cpu, i,ret = 0;
struct sched_param param = { .sched_priority =0 };
struct sched_param param = { .sched_priority =0 };
struct device_node *parent;
u32 temp_gpios[2];
ft_printk_info("%s\n",__FUNCTION__);
@@ -976,21 +967,27 @@ static int __init rk_ft_tests_init(void)
,i,l1_tst_cnt[i],l2_cpy_cnt[i],ftt_tst_cnt[i],pi_tst_cnt[i],stp_task_num[i]);
}
if(of_property_read_u32_array(parent,"rockchip,ft_end_cnt",&ft_end_cnt,1))
if(of_property_read_u32_array(parent,"rockchip,ft_end_cnt",(u32 *)&ft_end_cnt,1))
{
printk("%s:ft_end_cnt error\n",__FUNCTION__);
return -1;
}
if(of_property_read_u32_array(parent,"rockchip,ft_vol_gpios",(u32 *)&temp_gpios[0],2))
{
printk("%s:no ft_vol_gpios info,so ft ctr vol is not support\n",__FUNCTION__);
}
else
{
ft_client_ready_pin=temp_gpios[0];
ft_client_idle_pin=temp_gpios[1];
ft_printk_info("ft_vol_gpio%x,%x\n",ft_client_ready_pin,ft_client_idle_pin);
}
//ddr_clk = clk_get(NULL, "clk_ddr");
//clk_set_rate(ddr_clk,0);
for(i=0;i<TST_SETUPS;i++)
{
sema_init(&sem_setups[i], 0);
@@ -1032,22 +1029,26 @@ static int __init rk_ft_tests_init(void)
static int rk_ft_tests_over(void)
{
int ret = 0;
//int gpio_ret,gpio_ret1;
rk_ft_tests_init();
#ifdef ENABLE_FT_TEST_GPIO
//return 0;
//int gpio_ret,gpio_ret1;
ret=rk_ft_tests_init();
if(ret)
{
printk("rk_ft_tests_init error\n");
while(1);
}
if(ft_client_ready_pin&&ft_client_ready_pin)
{
//GPIO0_A0
gpio_set_in_output(FT_CLIENT_READY_PIN,RKPM_GPIO_OUTPUT);
gpio_set_output_level(FT_CLIENT_READY_PIN,RKPM_GPIO_OUT_L);
gpio_set_in_output(FT_CLIENT_IDLE_PIN,RKPM_GPIO_INPUT);
pin_set_fun(FT_CLIENT_READY_PIN); //ready
pin_set_fun(FT_CLIENT_IDLE_PIN); // idle
#endif
gpio_set_in_output(ft_client_ready_pin,RKPM_GPIO_OUTPUT);
gpio_set_output_level(ft_client_ready_pin,RKPM_GPIO_OUT_L);
gpio_set_in_output(ft_client_idle_pin,RKPM_GPIO_INPUT);
pin_set_fun(ft_client_ready_pin); //ready
pin_set_fun(ft_client_idle_pin); // idle
}
ft_cpu_test_type0_check(0,"KERNEL");
ft_cpu_test_type1_check(1,"HSPEED");