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ASoC: codecs: rv1106_codec: add support properties to configure init gains
Add support init gains: MIC Gain ALC Gain (0dB: 0x06) Lineout Gain (0dB: 0x1a) 0dB (0x01) min: -9.0dB (0x00) min: -39.0dB (0x00) 20dB (0x02) max: +37.5dB (0x1f) max: +6.0dB (0x1f) 12dB (0x03) step: +1.5dB step: +1.5dB Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Change-Id: I827329e3b96c64a7a344dfc4094fea6d118503a5
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@@ -50,6 +50,8 @@
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#define ADCL (1 << 0)
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#define ADCR (1 << 1)
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#define NOT_SPECIFIED (-1)
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enum soc_id_e {
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SOC_RV1103 = 0x1103,
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SOC_RV1106 = 0x1106,
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@@ -97,6 +99,11 @@ struct rv1106_codec_priv {
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/* For the high pass filter */
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unsigned int hpf_cutoff;
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/* Specify init gains after codec startup */
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unsigned int init_mic_gain;
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unsigned int init_alc_gain;
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unsigned int init_lineout_gain;
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bool adc_enable;
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bool dac_enable;
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bool micbias_enable;
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@@ -1697,31 +1704,68 @@ out:
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static int rv1106_codec_default_gains(struct rv1106_codec_priv *rv1106)
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{
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int gainl, gainr;
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/**
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* MIC Gain
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* 0dB (0x01)
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* 20dB (0x02)
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* 12dB (0x03)
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*/
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if (rv1106->init_mic_gain == NOT_SPECIFIED) {
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gainl = ACODEC_ADC_L_MIC_GAIN_0DB;
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gainr = ACODEC_ADC_R_MIC_GAIN_0DB;
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} else {
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gainl = ((rv1106->init_mic_gain >> 4) & 0x03) << ACODEC_ADC_L_MIC_GAIN_SFT;
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gainr = ((rv1106->init_mic_gain >> 0) & 0x03) << ACODEC_ADC_R_MIC_GAIN_SFT;
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}
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/* Prepare ADC gains */
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/* vendor step 12, set MIC PGA default gains */
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regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL2,
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ACODEC_ADC_L_MIC_GAIN_MSK |
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ACODEC_ADC_R_MIC_GAIN_MSK,
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ACODEC_ADC_L_MIC_GAIN_20DB |
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ACODEC_ADC_R_MIC_GAIN_20DB); // TODO: using 20dB
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gainl | gainr);
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/**
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* ALC Gain (0dB: 0x06)
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* min: -9.0dB (0x00)
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* max: +37.5dB (0x1f)
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* step: +1.5dB
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*/
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if (rv1106->init_alc_gain == NOT_SPECIFIED) {
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gainl = ACODEC_ADC_L_ALC_GAIN_0DB;
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gainr = ACODEC_ADC_R_ALC_GAIN_0DB;
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} else {
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gainl = ((rv1106->init_alc_gain >> 4) & 0x1f);
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gainr = ((rv1106->init_alc_gain >> 0) & 0x1f);
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}
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/* vendor step 13, set ALC default gains */
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regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL4,
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ACODEC_ADC_L_ALC_GAIN_MSK,
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ACODEC_ADC_L_ALC_GAIN_0DB);
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gainl);
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regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL5,
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ACODEC_ADC_R_ALC_GAIN_MSK,
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ACODEC_ADC_R_ALC_GAIN_0DB);
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gainr);
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/* Prepare DAC gains */
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/* Step 19, set LINEOUT default gains */
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regmap_update_bits(rv1106->regmap, ACODEC_DAC_GAIN_SEL,
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ACODEC_DAC_DIG_GAIN_MSK,
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ACODEC_DAC_DIG_GAIN(ACODEC_DAC_DIG_0DB));
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ACODEC_DAC_DIG_GAIN(ACODEC_DAC_DIG_0DB)); /* The calibrated fixed gain */
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/**
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* Lineout Gain (0dB: 0x1a)
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* min: -39.0dB (0x00)
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* max: +6.0dB (0x1f)
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* step: +1.5dB
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*/
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if (rv1106->init_lineout_gain == NOT_SPECIFIED)
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gainl = ACODEC_DAC_LINEOUT_GAIN_0DB;
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else
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gainl = rv1106->init_lineout_gain & 0x1f;
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regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL2,
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ACODEC_DAC_LINEOUT_GAIN_MSK,
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ACODEC_DAC_LINEOUT_GAIN_0DB);
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gainl);
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return 0;
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}
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@@ -2065,6 +2109,15 @@ static int rv1106_platform_probe(struct platform_device *pdev)
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rv1106->reset = NULL;
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}
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rv1106->init_mic_gain = NOT_SPECIFIED;
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of_property_read_u32(np, "init-mic-gain", &rv1106->init_mic_gain);
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rv1106->init_alc_gain = NOT_SPECIFIED;
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of_property_read_u32(np, "init-alc-gain", &rv1106->init_alc_gain);
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rv1106->init_lineout_gain = NOT_SPECIFIED;
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of_property_read_u32(np, "init-lineout-gain", &rv1106->init_lineout_gain);
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rv1106->pa_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
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GPIOD_OUT_LOW);
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if (IS_ERR(rv1106->pa_ctl_gpio))
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