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ARM: dts: rk3228: clk: rename gpu clk name

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change gpu clk name aclk_gpu to clk_gpu.

Change-Id: I0ee1fc47b94d7459914c6040aa3bcfc616626a83
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
This commit is contained in:
zhangqing
2015-10-14 08:42:16 -07:00
committed by Gerrit Code Review
parent 298e89389d
commit 7ce90f99da
3 changed files with 11 additions and 11 deletions
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14
arch/arm/boot/dts/rk3228-clocks.dtsi
View File

@@ -1546,21 +1546,21 @@
#address-cells = <1>;
#size-cells = <1>;
aclk_gpu_div: aclk_gpu_div {
clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_gpu>;
clock-output-names = "aclk_gpu";
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
};
aclk_gpu: aclk_gpu_mux {
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <5 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
clock-output-names = "aclk_gpu";
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
@@ -1601,7 +1601,7 @@
testclk: testclk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 4>;
clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&aclk_gpu>, <&aclk_peri>, <&aclk_core>;
clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&clk_gpu>, <&aclk_peri>, <&aclk_core>;
clock-output-names = "testclk";
#clock-cells = <0>;
#clock-init-cells = <1>;
@@ -1883,7 +1883,7 @@
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&aclk_gpu>, <&aclk_gpu>;
<&clk_gpu>, <&clk_gpu>;
clock-output-names =
"clk_ddrphy", "clk4x_ddrphy",

4
arch/arm/boot/dts/rk3228-fpga.dts
View File

@@ -173,7 +173,7 @@
rockchip,clocks-init-parent =
<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
<&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
<&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
@@ -185,7 +185,7 @@
<&aclk_peri 250000000>, <&hclk_peri 125000000>,
<&pclk_peri 62500000>, <&clk_mac 125000000>,
<&aclk_iep 250000000>, <&hclk_vio 125000000>,
<&aclk_rga 250000000>, <&aclk_gpu 250000000>,
<&aclk_rga 250000000>, <&clk_gpu 250000000>,
<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
<&clk_vdec_cabac 250000000>;
/*

4
arch/arm/boot/dts/rk3228.dtsi
View File

@@ -90,7 +90,7 @@
rockchip,clocks-init-parent =
<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
<&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
<&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
@@ -102,7 +102,7 @@
<&aclk_peri 250000000>, <&hclk_peri 125000000>,
<&pclk_peri 62500000>, <&clk_mac 125000000>,
<&aclk_iep 250000000>, <&hclk_vio 125000000>,
<&aclk_rga 250000000>, <&aclk_gpu 250000000>,
<&aclk_rga 250000000>, <&clk_gpu 250000000>,
<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
<&clk_vdec_cabac 250000000>;
/*