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ARM: dts: rockchip: remove unused rk3228 dts files
There are old v3.10 dts and unsuitable for v4.4, we need to remove them. Change-Id: I070fb1fd5d513883f43dfbdab6f173e68fe48e72 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
committed by
Gerrit Code Review
Gerrit Code Review
parent
503e169bba
commit
7d36af23c5
File diff suppressed because it is too large
Load Diff
@@ -1,266 +0,0 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/rkfb/rk_fb.h>
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#include "skeleton.dtsi"
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#include "rk3228-clocks.dtsi"
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/ {
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compatible = "rockchip,rk3228";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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};
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gic: interrupt-controller@32010000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x32011000 0x1000>,
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<0x32012000 0x1000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x10000000>;
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};
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chosen {
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bootargs = "initrd=0x62000000,0x00180000 init=/init console=ttyFIQ0,115200 earlyprintk=uart8250-32bit,0x11030000";
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};
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aliases {
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serial2 = &uart_dbg;
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};
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uart_dbg: serial@11030000 {
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compatible = "rockchip,serial";
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reg = <0x11030000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&xin24m>, <&xin24m>;
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clock-names = "sclk_uart", "pclk_uart";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,signal-irq = <159>;
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rockchip,wake-irq = <0>;
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rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
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rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
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//status = "disabled";
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};
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ion {
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compatible = "rockchip,ion";
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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ion_carveout: rockchip,ion-heap@2 {
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compatible = "rockchip,ion-heap";
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rockchip,ion_heap = <2>;
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reg = <0x42000000 0xc00000>;
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};
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*/
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ion_cma: rockchip,ion-heap@4 {
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compatible = "rockchip,ion-heap";
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rockchip,ion_heap = <4>;
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reg = <0x00000000 0x4000000>;
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};
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rockchip,ion-heap@0 { /* VMALLOC HEAP */
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compatible = "rockchip,ion-heap";
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rockchip,ion_heap = <0>;
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};
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240
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239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220
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219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
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199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180
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179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
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159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140
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139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120
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119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
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99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70
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69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
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39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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9 8 7 6 5 4 3 2 1 0>;
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default-brightness-level = <200>;
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};
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vop: vop@20020000 {
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compatible = "rockchip,rk3228-lcdc";
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backlight = <&backlight>;
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rockchip,cabc_mode = <0>;
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rockchip,prop = <1>;
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rockchip,pwr18 = <0>;
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rockchip,iommu-enabled = <1>;
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reg = <0x20050000 0x300>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
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clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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};
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vop_mmu {
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dbgname = "vop";
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compatible = "rockchip,vop_mmu";
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reg = <0x20053f00 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vopb_mmu";
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};
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fb: fb{
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compatible = "rockchip,rk-fb";
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rockchip,disp-mode = <0>;
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};
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rk_screen: rk_screen{
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compatible = "rockchip,screen";
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disp_timings: display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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screen-type = <SCREEN_RGB>;
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out-face = <OUT_P888>;
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clock-frequency = <27000000>;
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hactive = <800>;
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vactive = <480>;
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hback-porch = <206>;
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hfront-porch = <40>;
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vback-porch = <25>;
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vfront-porch = <10>;
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hsync-len = <10>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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swap-rb = <0>;
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swap-rg = <0>;
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swap-gb = <0>;
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};
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};
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};
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rockchip_clocks_init: clocks-init{
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compatible = "rockchip,clocks-init";
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rockchip,clocks-init-parent =
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<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
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<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
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<&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
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<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
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<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
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<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
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<&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
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rockchip,clocks-init-rate =
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<&clk_gpll 600000000>, <&clk_core 700000000>,
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<&clk_cpll 500000000>, <&aclk_bus 250000000>,
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<&hclk_bus 125000000>, <&pclk_bus 62500000>,
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<&aclk_peri 250000000>, <&hclk_peri 125000000>,
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<&pclk_peri 62500000>, <&clk_mac 125000000>,
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<&aclk_iep 250000000>, <&hclk_vio 125000000>,
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<&aclk_rga 250000000>, <&clk_gpu 250000000>,
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<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
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<&clk_vdec_cabac 250000000>;
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/*
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rockchip,clocks-uboot-has-init =
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<&aclk_vio0>;
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*/
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};
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rockchip_clocks_enable: clocks-enable {
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compatible = "rockchip,clocks-enable";
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clocks =
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/*PLL*/
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<&clk_apll>,
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<&clk_dpll>,
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<&clk_gpll>,
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<&clk_cpll>,
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/*PD_CORE*/
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<&clk_core>,
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<&pclk_dbg>,
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<&aclk_core>,
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<&clk_gates4 2>,
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/*PD_BUS*/
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<&aclk_bus>,
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<&hclk_bus>,
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<&pclk_bus>,
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<&clk_gates8 0>,/*aclk_intmem*/
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<&clk_gates8 1>,/*clk_intmem_mbist*/
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<&clk_gates8 2>,/*aclk_dmac_bus*/
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<&clk_gates10 1>,/*g_aclk_bus*/
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<&clk_gates13 9>,/*aclk_gic400*/
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<&clk_gates8 3>,/*hclk_rom*/
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<&clk_gates8 4>,/*pclk_ddrupctl*/
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<&clk_gates8 6>,/*pclk_ddrmon*/
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<&clk_gates9 4>,/*pclk_timer0*/
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<&clk_gates9 5>,/*pclk_stimer*/
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<&clk_gates10 0>,/*pclk_grf*/
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<&clk_gates10 4>,/*pclk_cru*/
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<&clk_gates10 6>,/*pclk_sgrf*/
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<&clk_gates10 3>,/*pclk_ddrphy*/
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<&clk_gates10 9>,/*pclk_phy_noc*/
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/*PD_PERI*/
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<&aclk_peri>,
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<&hclk_peri>,
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<&pclk_peri>,
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<&clk_gates12 0>,/*aclk_peri_noc*/
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<&clk_gates12 1>,/*hclk_peri_noc*/
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<&clk_gates12 2>,/*pclk_peri_noc*/
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<&clk_gates6 5>, /* g_clk_timer0 */
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<&clk_gates6 6>, /* g_clk_timer1 */
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<&clk_gates7 14>, /* g_aclk_gpu */
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<&clk_gates7 15>, /* g_aclk_gpu_noc */
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<&clk_gates1 3>;/*clk_jtag*/
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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pdma: pdma@110f0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x110f0000 0x4000>;
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clocks = <&clk_gates8 2>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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};
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};
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};
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@@ -1,295 +0,0 @@
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/dts-v1/;
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#include "rk3228.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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chosen {
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bootargs = "vmalloc=496M psci=enable";
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};
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fiq-debugger {
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status = "disabled";
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};
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wireless-wlan {
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compatible = "wlan-platdata";
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/* wifi_chip_type - wifi chip define
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* bcmwifi ==> like ap6xxx, rk90x;
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* rtkwifi ==> like rtl8188xx, rtl8723xx,rtl8812auv;
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* esp8089 ==> esp8089;
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* other ==> for other wifi;
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*/
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wifi_chip_type = "bcmwifi";
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sdio_vref = <1800>; //1800mv or 3300mv
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//keep_wifi_power_on;
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//power_ctrl_by_pmu;
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power_pmu_regulator = "act_ldo3";
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power_pmu_enable_level = <1>; //1->HIGH, 0->LOW
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//vref_ctrl_enable;
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//vref_ctrl_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
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vref_pmu_regulator = "act_ldo3";
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vref_pmu_enable_level = <1>; //1->HIGH, 0->LOW
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WIFI,poweren_gpio = <&gpio2 GPIO_D2 GPIO_ACTIVE_HIGH>;
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WIFI,host_wake_irq = <&gpio0 GPIO_D4 GPIO_ACTIVE_HIGH>;
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//WIFI,reset_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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wireless-bluetooth {
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compatible = "bluetooth-platdata";
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//wifi-bt-power-toggle;
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//uart_rts_gpios = <&gpio2 GPIO_D5 GPIO_ACTIVE_LOW>;
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//pinctrl-names = "default","rts_gpio";
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//pinctrl-0 = <&uart1_rts>;
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//pinctrl-1 = <&uart1_rts_gpio>;
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//BT,power_gpio = <&gpio4 GPIO_D3 GPIO_ACTIVE_HIGH>;
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BT,reset_gpio = <&gpio2 GPIO_D5 GPIO_ACTIVE_HIGH>;
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BT,wake_gpio = <&gpio3 GPIO_D3 GPIO_ACTIVE_HIGH>;
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BT,wake_host_irq = <&gpio3 GPIO_D2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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pwm-regulator1 {
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compatible = "rockchip_pwm_regulator";
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pwms = <&pwm1 0 2000>;
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rockchip,pwm_id= <1>;
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rockchip,pwm_voltage_map= <950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000 1400000>;
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rockchip,pwm_voltage= <1100000>;
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rockchip,pwm_min_voltage= <950000>;
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rockchip,pwm_max_voltage= <1450000>;
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rockchip,pwm_suspend_voltage= <950000>;
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rockchip,pwm_coefficient= <475>;
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status = "okay";
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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pwm_reg0: regulator@0 {
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regulator-compatible = "pwm_dcdc1";
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regulator-name= "vdd_arm";
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <1450000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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};
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pwm-regulator2 {
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compatible = "rockchip_pwm_regulator";
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pwms = <&pwm2 0 25000>;
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rockchip,pwm_id= <2>;
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rockchip,pwm_voltage_map= <1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000>;
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rockchip,pwm_voltage= <1200000>;
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rockchip,pwm_min_voltage= <1000000>;
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rockchip,pwm_max_voltage= <1300000>;
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rockchip,pwm_suspend_voltage= <1250000>;
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rockchip,pwm_coefficient= <475>;
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status = "okay";
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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pwm_reg1: regulator@1 {
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regulator-compatible = "pwm_dcdc2";
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regulator-name= "vdd_logic";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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};
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};
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&nandc {
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status = "okay"; //used nand set "okay" ,used emmc set "disabled"
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};
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&emmc {
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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supports-highspeed;
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supports-emmc;
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bootpart-no-access;
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supports-DDR_MODE;
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ignore-pm-notify;
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keep-power-in-suspend;
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status = "okay";
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};
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&sdmmc {
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clock-frequency = <37500000>;
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clock-freq-min-max = <400000 37500000>;
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supports-highspeed;
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supports-sd;
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broken-cd;
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card-detect-delay = <200>;
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ignore-pm-notify;
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keep-power-in-suspend;
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status = "okay";
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};
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&sdio {
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clock-frequency = <37500000>;
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clock-freq-min-max = <200000 37500000>;
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supports-highspeed;
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supports-sdio;
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ignore-pm-notify;
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keep-power-in-suspend;
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cap-sdio-irq;
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status = "okay";
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};
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&uart1{
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status = "okay";
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dma-names = "!tx", "!rx";
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//pinctrl-0 = <&uart1_xfer &uart1_cts>;
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};
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&i2c0 {
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status = "okay";
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rtc@51 {
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compatible = "rtc,hym8563";
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reg = <0x51>;
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irq_gpio = <&gpio0 GPIO_A4 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&pwm1 {
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status = "okay";
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};
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|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Due to not have the software of PWM for remotectrl.
|
||||
* We can _*HACK*_ do that as the following.
|
||||
*/
|
||||
&pwm3 {
|
||||
compatible = "rockchip,remotectl-pwm";
|
||||
remote_pwm_id = <3>;
|
||||
handle_cpu_id = <1>;
|
||||
status = "okay";
|
||||
|
||||
ir_key1{
|
||||
rockchip,usercode = <0x4040>;
|
||||
rockchip,key_table =
|
||||
<0xf2 KEY_REPLY>,
|
||||
<0xba KEY_BACK>,
|
||||
<0xf4 KEY_UP>,
|
||||
<0xf1 KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xee KEY_RIGHT>,
|
||||
<0xbd KEY_HOME>,
|
||||
<0xea KEY_VOLUMEUP>,
|
||||
<0xe3 KEY_VOLUMEDOWN>,
|
||||
<0xe2 KEY_SEARCH>,
|
||||
<0xb2 KEY_POWER>,
|
||||
<0xbc KEY_MUTE>,
|
||||
<0xec KEY_MENU>,
|
||||
<0xbf 0x190>,
|
||||
<0xe0 0x191>,
|
||||
<0xe1 0x192>,
|
||||
<0xe9 183>,
|
||||
<0xe6 248>,
|
||||
<0xe8 185>,
|
||||
<0xe7 186>,
|
||||
<0xf0 388>,
|
||||
<0xbe 0x175>;
|
||||
};
|
||||
ir_key2{
|
||||
rockchip,usercode = <0xff00>;
|
||||
rockchip,key_table =
|
||||
<0xf9 KEY_HOME>,
|
||||
<0xbf KEY_BACK>,
|
||||
<0xfb KEY_MENU>,
|
||||
<0xaa KEY_REPLY>,
|
||||
<0xb9 KEY_UP>,
|
||||
<0xe9 KEY_DOWN>,
|
||||
<0xb8 KEY_LEFT>,
|
||||
<0xea KEY_RIGHT>,
|
||||
<0xeb KEY_VOLUMEDOWN>,
|
||||
<0xef KEY_VOLUMEUP>,
|
||||
<0xf7 KEY_MUTE>,
|
||||
<0xe7 KEY_POWER>,
|
||||
<0xfc KEY_POWER>,
|
||||
<0xa9 KEY_VOLUMEDOWN>,
|
||||
<0xa8 KEY_VOLUMEDOWN>,
|
||||
<0xe0 KEY_VOLUMEDOWN>,
|
||||
<0xa5 KEY_VOLUMEDOWN>,
|
||||
<0xab 183>,
|
||||
<0xb7 388>,
|
||||
<0xf8 184>,
|
||||
<0xaf 185>,
|
||||
<0xed KEY_VOLUMEDOWN>,
|
||||
<0xee 186>,
|
||||
<0xb3 KEY_VOLUMEDOWN>,
|
||||
<0xf1 KEY_VOLUMEDOWN>,
|
||||
<0xf2 KEY_VOLUMEDOWN>,
|
||||
<0xf3 KEY_SEARCH>,
|
||||
<0xb4 KEY_VOLUMEDOWN>,
|
||||
<0xbe KEY_SEARCH>;
|
||||
};
|
||||
ir_key3{
|
||||
rockchip,usercode = <0x1dcc>;
|
||||
rockchip,key_table =
|
||||
<0xee KEY_REPLY>,
|
||||
<0xf0 KEY_BACK>,
|
||||
<0xf8 KEY_UP>,
|
||||
<0xbb KEY_DOWN>,
|
||||
<0xef KEY_LEFT>,
|
||||
<0xed KEY_RIGHT>,
|
||||
<0xfc KEY_HOME>,
|
||||
<0xf1 KEY_VOLUMEUP>,
|
||||
<0xfd KEY_VOLUMEDOWN>,
|
||||
<0xb7 KEY_SEARCH>,
|
||||
<0xff KEY_POWER>,
|
||||
<0xf3 KEY_MUTE>,
|
||||
<0xbf KEY_MENU>,
|
||||
<0xf9 0x191>,
|
||||
<0xf5 0x192>,
|
||||
<0xb3 388>,
|
||||
<0xbe KEY_1>,
|
||||
<0xba KEY_2>,
|
||||
<0xb2 KEY_3>,
|
||||
<0xbd KEY_4>,
|
||||
<0xf9 KEY_5>,
|
||||
<0xb1 KEY_6>,
|
||||
<0xfc KEY_7>,
|
||||
<0xf8 KEY_8>,
|
||||
<0xb0 KEY_9>,
|
||||
<0xb6 KEY_0>,
|
||||
<0xb5 KEY_BACKSPACE>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac_clkin {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&gmac {
|
||||
/* pmu_regulator = "act_ldo5"; */
|
||||
/* power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>; */
|
||||
/* reset-gpio = <&gpio3 GPIO_B4 GPIO_ACTIVE_LOW>; */
|
||||
/* phyirq-gpio = <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>; */
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rmii_pins>;
|
||||
clock_in_out = "input";
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,38 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2014-2015 ROCKCHIP, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <dt-bindings/clock/ddr.h>
|
||||
#include <dt-bindings/dram/rockchip,rk3368.h>
|
||||
|
||||
/ {
|
||||
dram_timing: dram_timing {
|
||||
compatible = "rockchip,dram-timing";
|
||||
dram_spd_bin = <DDR3_DEFAULT>;
|
||||
sr_idle = <1>;
|
||||
pd_idle = <0x20>;
|
||||
dram_dll_disb_freq = <300>;
|
||||
phy_dll_disb_freq = <400>;
|
||||
dram_odt_disb_freq = <333>;
|
||||
phy_odt_disb_freq = <333>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
lpddr3_drv = <LP3_DS_34ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
lpddr2_drv = <LP2_DS_34ohm>;
|
||||
/* lpddr2 not supported odt */
|
||||
phy_clk_drv = <PHY_RON_45ohm>;
|
||||
phy_cmd_drv = <PHY_RON_34ohm>;
|
||||
phy_dqs_drv = <PHY_RON_34ohm>;
|
||||
phy_odt = <PHY_RTT_279ohm>;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user