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lcd: add clk frac shift support [2/2]

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PD#SWPL-17480

Problem:
sometime there need shift a little for frac

Solution:
add clk frac shift support

Verify:
x301

Change-Id: I937cca1b07f20d95144d1b85addc2cac775d1aac
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2019-11-26 23:14:40 +08:00
committed by Chris
parent 6bba961370
commit 7d8b199666
4 changed files with 406 additions and 326 deletions
Download Patch File Download Diff File Expand all files Collapse all files

718
drivers/amlogic/media/vout/lcd/lcd_clk_config.c
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File diff suppressed because it is too large Load Diff

6
drivers/amlogic/media/vout/lcd/lcd_clk_config.h
View File

@@ -25,6 +25,10 @@
* clk config
* **********************************
*/
#define LCD_PLL_MODE_DEFAULT BIT(0)
#define LCD_PLL_MODE_SPECIAL_CNTL BIT(1)
#define LCD_PLL_MODE_FRAC_SHIFT BIT(2)
#define PLL_RETRY_MAX 20
#define LCD_CLK_CTRL_EN 0
#define LCD_CLK_CTRL_RST 1
@@ -49,6 +53,7 @@ struct lcd_clk_data_s {
unsigned int pll_n_max;
unsigned int pll_n_min;
unsigned int pll_frac_range;
unsigned int pll_frac_sign_bit;
unsigned int pll_od_sel_max;
unsigned int pll_ref_fmax;
unsigned int pll_ref_fmin;
@@ -102,6 +107,7 @@ struct lcd_clk_config_s { /* unit: kHz */
unsigned int pll_tcon_div_sel;
unsigned int pll_level;
unsigned int pll_frac;
unsigned int pll_frac_half_shift;
unsigned int pll_fout;
unsigned int ss_level;
unsigned int ss_freq;

7
drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
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@@ -44,6 +44,7 @@
#define PLL_N_MIN_GXL 1
#define PLL_N_MAX_GXL 1
#define PLL_FRAC_RANGE_GXL (1 << 10)
#define PLL_FRAC_SIGN_BIT_GXL 11
#define PLL_OD_SEL_MAX_GXL 3
#define PLL_FREF_MIN_GXL (5 * 1000)
#define PLL_FREF_MAX_GXL (25 * 1000)
@@ -78,6 +79,7 @@
#define PLL_N_MIN_TXL 1
#define PLL_N_MAX_TXL 1
#define PLL_FRAC_RANGE_TXL (1 << 10)
#define PLL_FRAC_SIGN_BIT_TXL 11
#define PLL_OD_SEL_MAX_TXL 3
#define PLL_FREF_MIN_TXL (5 * 1000)
#define PLL_FREF_MAX_TXL (25 * 1000)
@@ -112,6 +114,7 @@
#define PLL_N_MIN_TXLX 1
#define PLL_N_MAX_TXLX 1
#define PLL_FRAC_RANGE_TXLX (1 << 10)
#define PLL_FRAC_SIGN_BIT_TXLX 11
#define PLL_OD_SEL_MAX_TXLX 3
#define PLL_FREF_MIN_TXLX (5 * 1000)
#define PLL_FREF_MAX_TXLX (25 * 1000)
@@ -143,6 +146,7 @@
#define PLL_N_MIN_AXG 1
#define PLL_N_MAX_AXG 1
#define PLL_FRAC_RANGE_AXG (1 << 10)
#define PLL_FRAC_SIGN_BIT_AXG 11
#define PLL_OD_SEL_MAX_AXG 3
#define PLL_FREF_MIN_AXG (5 * 1000)
#define PLL_FREF_MAX_AXG (25 * 1000)
@@ -166,6 +170,7 @@
/* ******** frequency limit (unit: kHz) ******** */
#define PLL_OD_FB_GP0_G12A 0
#define PLL_FRAC_RANGE_GP0_G12A (1 << 17)
#define PLL_FRAC_SIGN_BIT_GP0_G12A 18
#define PLL_OD_SEL_MAX_GP0_G12A 5
#define PLL_VCO_MIN_GP0_G12A (3000 * 1000)
#define PLL_VCO_MAX_GP0_G12A (6000 * 1000)
@@ -184,6 +189,7 @@
/* ******** frequency limit (unit: kHz) ******** */
#define PLL_OD_FB_HPLL_G12A 0
#define PLL_FRAC_RANGE_HPLL_G12A (1 << 17)
#define PLL_FRAC_SIGN_BIT_HPLL_G12A 18
#define PLL_OD_SEL_MAX_HPLL_G12A 3
#define PLL_VCO_MIN_HPLL_G12A (3000 * 1000)
#define PLL_VCO_MAX_HPLL_G12A (6000 * 1000)
@@ -223,6 +229,7 @@
#define PLL_N_MIN_TL1 1
#define PLL_N_MAX_TL1 1
#define PLL_FRAC_RANGE_TL1 (1 << 17)
#define PLL_FRAC_SIGN_BIT_TL1 18
#define PLL_OD_SEL_MAX_TL1 3
#define PLL_FREF_MIN_TL1 (5 * 1000)
#define PLL_FREF_MAX_TL1 (25 * 1000)

1
include/linux/amlogic/media/vout/lcd/lcd_vout.h
View File

@@ -62,6 +62,7 @@ extern unsigned char lcd_debug_print_flag;
/* ******** clk_ctrl ******** */
#define CLK_CTRL_LEVEL 28 /* [30:28] */
#define CLK_CTRL_FRAC_SHIFT 24 /* [24] */
#define CLK_CTRL_FRAC 0 /* [18:0] */
/* **********************************