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camera: rockchip: camsys_drv: 0.0x21.0xe

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1) correct mipiphy_hsfreqrange of 3368.
2) add csi-phy timing setting for 3368.

Change-Id: Ia5203dcd8f01bc8989d5bb41a1b2af71bb91f607
Signed-off-by: dalong.zhang <dalon.zhang@rock-chips.com>
This commit is contained in:
dalong.zhang
2017-05-02 21:58:55 +08:00
committed by Huang, Tao
parent 436523aab0
commit 7daa21f818
5 changed files with 62 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/media/video/rk_camsys/camsys_internal.h
View File

@@ -159,8 +159,11 @@
1) support rk3288.
*v0.0x21.0xd:
1) modify mipiphy_hsfreqrange for 3368.
*v0.0x21.0xe
1) correct mipiphy_hsfreqrange of 3368.
2) add csi-phy timing setting for 3368.
*/
#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x21, 0xd)
#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0, 0x21, 0xe)
#define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys"
#define CAMSYS_PLATFORM_MARVIN_NAME "Platform_MarvinDev"

37
drivers/media/video/rk_camsys/camsys_soc_rk3366.c
View File

@@ -19,11 +19,11 @@ static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
{500, 600, 0x07},
{600, 700, 0x08},
{700, 800, 0x09},
{800, 1000, 0x10},
{1000, 1200, 0x11},
{1200, 1400, 0x12},
{1400, 1600, 0x13},
{1600, 1800, 0x14}
{800, 1000, 0xa},
{1000, 1100, 0xb},
{1100, 1250, 0xc},
{1250, 1350, 0xd},
{1350, 1500, 0xe}
};
#if 0
@@ -127,6 +127,22 @@ camsys_mipiphy_soc_para_t *para)
| (1 << ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT));
*/
/* phy start */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
/* set data lane num and enable clock lane */
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET,
((para->phy->data_en_bit << 2) | (0x1 << 6) | 0x1));
/* Reset dphy analog part */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
usleep_range(500, 1000);
/* Reset dphy digital part */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
write_grf_reg(GRF_SOC_CON6_OFFSET,
MIPI_CSI_DPHY_RX_FORCERXMODE_MASK |
MIPI_CSI_DPHY_RX_FORCERXMODE_BIT);
write_csiphy_reg
((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
hsfreqrange |
@@ -155,11 +171,10 @@ camsys_mipiphy_soc_para_t *para)
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
+ 0x300) & (~0xf)));
}
/*set data lane num and enable clock lane */
write_csiphy_reg(0x00, ((para->phy->data_en_bit << 2)
| (0x1 << 6) | 0x1));
/*
* MIPI CTRL bit8:11 SHUTDOWN_LANE are invert
* connect to dphy pin_enable_x
*/
base =
(unsigned long)
para->camsys_dev->devmems.registermem->vir_base;
@@ -225,7 +240,7 @@ camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
else
__raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
MRV_AFM_BASE + VI_IRCL));
camsys_trace(1, "Isp self soft rst: %ld", reset);
camsys_trace(2, "Isp self soft rst: %ld", reset);
break;
}

3
drivers/media/video/rk_camsys/camsys_soc_rk3366.h
View File

@@ -89,6 +89,9 @@
*/
#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
#define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24)
#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (0 << 8)
#define CSIHOST_N_LANES_OFFSET 0x04
#define CSIHOST_N_LANES_OFFSET_BIT (0)

37
drivers/media/video/rk_camsys/camsys_soc_rk3368.c
View File

@@ -20,11 +20,11 @@ static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
{500, 600, 0x07},
{600, 700, 0x08},
{700, 800, 0x09},
{800, 1000, 0x10},
{1000, 1200, 0x11},
{1200, 1400, 0x12},
{1400, 1600, 0x13},
{1600, 1800, 0x14}
{800, 1000, 0xa},
{1000, 1100, 0xb},
{1100, 1250, 0xc},
{1250, 1350, 0xd},
{1350, 1500, 0xe}
};
#if 0
@@ -124,7 +124,23 @@ static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para)
write_grf_reg(GRF_SOC_CON6_OFFSET, ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK
| (1 << ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT));
/* phy start */
/* phy start */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
/* set data lane num and enable clock lane */
write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET,
((para->phy->data_en_bit << 2) | (0x1 << 6) | 0x1));
/* Reset dphy analog part */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
usleep_range(500, 1000);
/* Reset dphy digital part */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
write_grf_reg(GRF_SOC_CON6_OFFSET,
MIPI_CSI_DPHY_RX_FORCERXMODE_MASK |
MIPI_CSI_DPHY_RX_FORCERXMODE_BIT);
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
hsfreqrange |
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
@@ -152,11 +168,10 @@ static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para)
(read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
+ 0x300) & (~0xf)));
}
/*set data lane num and enable clock lane */
write_csiphy_reg(0x00, ((para->phy->data_en_bit << 2)
| (0x1 << 6) | 0x1));
/*
* MIPI CTRL bit8:11 SHUTDOWN_LANE are invert
* connect to dphy pin_enable_x
*/
base = (unsigned long)para->camsys_dev->devmems.registermem->vir_base;
*((unsigned int *)(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
&= ~(0x0f << 8);

3
drivers/media/video/rk_camsys/camsys_soc_rk3368.h
View File

@@ -89,6 +89,9 @@
*/
#define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
#define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24)
#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (0 << 8)
#define CSIHOST_N_LANES_OFFSET 0x04
#define CSIHOST_N_LANES_OFFSET_BIT (0)