shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: px30-evb-ext-rk618: Create a new dtsi for rk618

Browse Source 
Change-Id: I7511599eba331044f8e386dcc5d5840a1eec5457
Signed-off-by: Wu Jingchen <oven.wu@rock-chips.com>
This commit is contained in:
Wu Jingchen
2019-02-27 10:24:34 +08:00
committed by Tao Huang
parent 675c418862
commit 7e2c9c679c
3 changed files with 111 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
arch/arm64/boot/dts/rockchip/px30-evb-ext-rk618-avb.dts
View File

@@ -3,116 +3,13 @@
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/clock/rk618-cru.h>
#include <dt-bindings/display/media-bus-format.h>
#include "px30-evb-ddr3-v10.dtsi"
#include "px30-evb-ext-rk618.dtsi"
/ {
model = "Rockchip PX30 EVB EXT RK618 board";
compatible = "rockchip,px30-evb-ext-rk618-avb", "rockchip,px30";
};
&dmc {
auto-freq-en = <0>;
};
&vcc3v0_pmu {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-suspend-microvolt = <3300000>;
};
};
&i2c1 {
rk618@50 {
compatible = "rockchip,rk618";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";
clock: cru {
compatible = "rockchip,rk618-cru";
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
clock-names = "clkin", "lcdc0_dclkp";
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
<&clock VIF_PLLIN_CLK>,
<&clock SCALER_CLK>,
<&clock VIF0_PRE_CLK>,
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,
<&clock VIF0_CLK>;
#clock-cells = <1>;
status = "okay";
};
hdmi {
compatible = "rockchip,rk618-hdmi";
clocks = <&clock HDMI_CLK>;
clock-names = "hdmi";
assigned-clocks = <&clock HDMI_CLK>;
assigned-clock-parents = <&clock VIF0_CLK>;
interrupt-parent = <&gpio2>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_rgb: endpoint {
remote-endpoint = <&rgb_out_hdmi>;
};
};
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_rgb>;
};
};
};
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};
&firmware_android {
compatible = "android,firmware";
boot_devices = "ff390000.dwmmc,ff3b0000.nandc";

105
arch/arm64/boot/dts/rockchip/px30-evb-ext-rk618.dts
View File

@@ -4,116 +4,13 @@
*/
/dts-v1/;
#include <dt-bindings/clock/rk618-cru.h>
#include <dt-bindings/display/media-bus-format.h>
#include "px30-evb-ddr3-v10.dtsi"
#include "px30-evb-ext-rk618.dtsi"
/ {
model = "Rockchip PX30 EVB EXT RK618 board";
compatible = "rockchip,px30-evb-ext-rk618", "rockchip,px30";
};
&dmc {
auto-freq-en = <0>;
};
&vcc3v0_pmu {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-suspend-microvolt = <3300000>;
};
};
&i2c1 {
status = "okay";
rk618@50 {
compatible = "rockchip,rk618";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";
clock: cru {
compatible = "rockchip,rk618-cru";
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
clock-names = "clkin", "lcdc0_dclkp";
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
<&clock VIF_PLLIN_CLK>,
<&clock SCALER_CLK>,
<&clock VIF0_PRE_CLK>,
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,
<&clock VIF0_CLK>;
#clock-cells = <1>;
status = "okay";
};
hdmi {
compatible = "rockchip,rk618-hdmi";
clocks = <&clock HDMI_CLK>;
clock-names = "hdmi";
assigned-clocks = <&clock HDMI_CLK>;
assigned-clock-parents = <&clock VIF0_CLK>;
interrupt-parent = <&gpio2>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_rgb: endpoint {
remote-endpoint = <&rgb_out_hdmi>;
};
};
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_rgb>;
};
};
};
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};
&firmware_android {
compatible = "android,firmware";
fstab {

109
arch/arm64/boot/dts/rockchip/px30-evb-ext-rk618.dtsi Normal file
View File

@@ -0,0 +1,109 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/clock/rk618-cru.h>
#include <dt-bindings/display/media-bus-format.h>
#include "px30-evb-ddr3-v10.dtsi"
&dmc {
auto-freq-en = <0>;
};
&vcc3v0_pmu {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-suspend-microvolt = <3300000>;
};
};
&i2c1 {
rk618@50 {
compatible = "rockchip,rk618";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "clkin";
assigned-clocks = <&cru SCLK_I2S1_OUT>;
assigned-clock-rates = <12000000>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
status = "okay";
clock: cru {
compatible = "rockchip,rk618-cru";
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
clock-names = "clkin", "lcdc0_dclkp";
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
<&clock VIF_PLLIN_CLK>,
<&clock SCALER_CLK>,
<&clock VIF0_PRE_CLK>,
<&clock CODEC_CLK>,
<&clock DITHER_CLK>;
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
<&clock LCDC0_CLK>,
<&clock SCALER_PLL_CLK>,
<&clock VIF_PLL_CLK>,
<&cru SCLK_I2S1_OUT>,
<&clock VIF0_CLK>;
#clock-cells = <1>;
status = "okay";
};
hdmi {
compatible = "rockchip,rk618-hdmi";
clocks = <&clock HDMI_CLK>;
clock-names = "hdmi";
assigned-clocks = <&clock HDMI_CLK>;
assigned-clock-parents = <&clock VIF0_CLK>;
interrupt-parent = <&gpio2>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_rgb: endpoint {
remote-endpoint = <&rgb_out_hdmi>;
};
};
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_rgb>;
};
};
};
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};