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dt-bindings: clock: rk3568: update the pcie soft reset id

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Updates missing parts of the TRM.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia24cd2986f7b0f11884260132aa4f5782eb58c52
This commit is contained in:
Elaine Zhang
2020-11-12 15:31:31 +08:00
parent b86361fa4e
commit 7e7e372271
1 changed files with 30 additions and 0 deletions
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30
include/dt-bindings/clock/rk3568-cru.h
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@@ -631,12 +631,42 @@
/* cru_softrst_con10 */
#define SRST_P_PCIE20 160
#define SRST_PCIE20_POWERUP 161
#define SRST_MSTR_ARESET_PCIE20 162
#define SRST_SLV_ARESET_PCIE20 163
#define SRST_DBI_ARESET_PCIE20 164
#define SRST_BRESET_PCIE20 165
#define SRST_PERST_PCIE20 166
#define SRST_CORE_RST_PCIE20 167
#define SRST_NSTICKY_RST_PCIE20 168
#define SRST_STICKY_RST_PCIE20 169
#define SRST_PWR_RST_PCIE20 170
/* cru_softrst_con11 */
#define SRST_P_PCIE30X1 176
#define SRST_PCIE30X1_POWERUP 177
#define SRST_M_ARESET_PCIE30X1 178
#define SRST_S_ARESET_PCIE30X1 179
#define SRST_D_ARESET_PCIE30X1 180
#define SRST_BRESET_PCIE30X1 181
#define SRST_PERST_PCIE30X1 182
#define SRST_CORE_RST_PCIE30X1 183
#define SRST_NSTC_RST_PCIE30X1 184
#define SRST_STC_RST_PCIE30X1 185
#define SRST_PWR_RST_PCIE30X1 186
/* cru_softrst_con12 */
#define SRST_P_PCIE30X2 192
#define SRST_PCIE30X2_POWERUP 193
#define SRST_M_ARESET_PCIE30X2 194
#define SRST_S_ARESET_PCIE30X2 195
#define SRST_D_ARESET_PCIE30X2 196
#define SRST_BRESET_PCIE30X2 197
#define SRST_PERST_PCIE30X2 198
#define SRST_CORE_RST_PCIE30X2 199
#define SRST_NSTC_RST_PCIE30X2 200
#define SRST_STC_RST_PCIE30X2 201
#define SRST_PWR_RST_PCIE30X2 202
/* cru_softrst_con13 */
#define SRST_A_PHP_NIU 208