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arm64: dts: rockchip: rk3588s: Add hdptxphy0 node

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Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I7e0ffe2338ac26c7c006312d5689d5f6f3fbebea
This commit is contained in:
Wyon Bi
2021-09-22 10:44:20 +08:00
committed by Tao Huang
parent bfc9c2149e
commit 7efebce0d3
1 changed files with 21 additions and 0 deletions
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21
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -448,6 +448,11 @@
};
};
hdptxphy0_grf: syscon@fd5e0000 {
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
reg = <0x0 0xfd5e0000 0x0 0x80>;
};
ioc: syscon@fd5f0000 {
compatible = "rockchip,rk3588-ioc", "syscon";
reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2088,6 +2093,22 @@
arm,pl330-periph-burst;
};
hdptxphy0: phy@fed60000 {
compatible = "rockchip,rk3588-hdptx-phy";
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
<&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
<&cru SRST_HDPTX0_LCPLL>;
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
"lcpll";
rockchip,grf = <&hdptxphy0_grf>;
#phy-cells = <0>;
status = "disabled";
};
usbdp_phy0: phy@fed80000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed80000 0x0 0x10000>;