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ath10k: Get rid of "per_ce_irq" hw param
As of the patch ("ath10k: Keep track of which interrupts fired, don't
poll them") we now have no users of this hardware parameter. Remove
it.
Suggested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200709082024.v2.2.I083faa4e62e69f863311c89ae5eb28ec5a229b70@changeid
This commit is contained in:
committed by
Kalle Valo
parent
d66d24ac30
commit
7f86551665
@@ -119,7 +119,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -155,7 +154,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -220,7 +218,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -255,7 +252,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -290,7 +286,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -328,7 +323,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -370,7 +364,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -418,7 +411,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -463,7 +455,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -498,7 +489,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -535,7 +525,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -604,7 +593,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = 0x20,
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.target_64bit = false,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
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.per_ce_irq = false,
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.shadow_reg_support = false,
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.rri_on_ddr = false,
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.hw_filter_reset_required = true,
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@@ -632,7 +620,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
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.target_64bit = true,
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.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
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.per_ce_irq = true,
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.shadow_reg_support = true,
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.rri_on_ddr = true,
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.hw_filter_reset_required = false,
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@@ -593,9 +593,6 @@ struct ath10k_hw_params {
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/* Target rx ring fill level */
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u32 rx_ring_fill_level;
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/* target supporting per ce IRQ */
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bool per_ce_irq;
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/* target supporting shadow register for ce write */
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bool shadow_reg_support;
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