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hdmitx: fix no display under frac_mode

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PD#166241: hdmitx: fix no display under frac_mode

1.update pll parameters
2.4k60hz444/rgb8bit doesn't frac_mode

Change-Id: I45c8bade4cd8f83a7b4d36aadbdbbaa9dfca32f1
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
This commit is contained in:
Yi Zhou
2018-05-18 12:41:38 +08:00
committed by Yixun Lan
parent b9c7a6084e
commit 7f86bf6643
3 changed files with 43 additions and 16 deletions
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14
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
View File

@@ -333,6 +333,7 @@ static struct frac_rate_table fr_tab[] = {
static void recalc_vinfo_sync_duration(struct vinfo_s *info, unsigned int frac)
{
struct frac_rate_table *fr = &fr_tab[0];
struct hdmitx_dev *hdev = &hdmitx_device;
pr_info(SYS "recalc before %s %d %d\n", info->name,
info->sync_duration_num, info->sync_duration_den);
@@ -346,6 +347,19 @@ static void recalc_vinfo_sync_duration(struct vinfo_s *info, unsigned int frac)
info->sync_duration_num = fr->sync_num_int;
info->sync_duration_den = fr->sync_den_int;
}
if (hdev->chip_type == MESON_CPU_ID_G12A)
if ((hdev->cur_VIC ==
HDMI_3840x2160p60_16x9) ||
(hdev->cur_VIC ==
HDMI_4096x2160p60_256x135))
if (hdev->para->cs !=
COLORSPACE_YUV420) {
info->sync_duration_num
= fr->sync_num_int;
info->sync_duration_den
= fr->sync_den_int;
}
break;
}
fr++;

12
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -999,9 +999,15 @@ static void hdmitx_check_frac_rate(struct hdmitx_dev *hdev)
frac_rate = hdev->frac_rate_policy;
para = hdmi_get_fmt_paras(vic);
if (para && (para->name) && likely_frac_rate_mode(para->name))
;
else {
if (para && (para->name) && likely_frac_rate_mode(para->name)) {
if (hdev->chip_type == MESON_CPU_ID_G12A)
if ((vic == HDMI_3840x2160p60_16x9) ||
(vic == HDMI_4096x2160p60_256x135))
if (para->cs != COLORSPACE_YUV420) {
pr_info("g12a 6GHz doesn't have frac_rate\n");
frac_rate = 0;
}
} else {
pr_info("%s doesn't have frac_rate\n", para->name);
frac_rate = 0;
}

33
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -94,9 +94,15 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val)
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
if (frac_val == 0x8148) {
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x44331290);
} else {
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
}
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
@@ -149,13 +155,14 @@ static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
{
switch (clk) {
case 5940000:
if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8168 : 0x10000))
if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
break;
else if (set_hpll_hclk_v2(0x7b, frac_rate ? 0x140b4 : 0x18000))
break;
else if (set_hpll_hclk_v3(0xf7, frac_rate ? 0x8168 : 0x10000))
else if (set_hpll_hclk_v3(0xf7, frac_rate ? 0x8148 : 0x10000))
break;
else
break;
@@ -182,10 +189,10 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
@@ -212,10 +219,10 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));