Merge commit '559aa0ed870d95d91c14d3471747aa5979d7655a'

* commit '559aa0ed870d95d91c14d3471747aa5979d7655a': (27 commits) pwm: rockchip-test: Add demo for updating both period and duty in wave generator mode pwm: rockchip: simplify to one wave_table configuration instead of duty_table and period_table media: rockchip: vicap support get data type form sensor driver include: rk-camera-module: add cmd of RKMODULE_GET_SPD_RATIO include: rk-camera-module: add cmd of RKMODULE_SET_BLC include: rk-camera-module: add cmd of RKMODULE_SET_WB_GAIN ASoC: codecs: rk_dsm: Fixed the configuration in multi codec sound was modified by capture stream drm/rockchip: vop2: Set post-csc input range limited when vp is yuv overlay clk: rockchip: rv1126b: fix hclk_rkrng_ns parent gpio: rockchip: Fix debounce clock management and refcount handling driver: rknpu: Fix missing misc_deregister() on dma heap open failure media: rockchip: isp: default to NO_HDR if sensor Unimplemented RKMODULE_GET_HDR_CFG video: rockchip: mpp: rkvdec2: fix vdec IP stuck issue ARM: dts: rockchip: update the init values of the ili9881d screen for all platforms that use it arm64: dts: rockchip: rv1126bp-evb: update dsi panel configuration media: rockchip: isp: fix isp35 bls3 video: rockchip: vehicle: fix generic sensor read data error arm64: dts: rockchip: rk3576-vehicle-evb: close dmc default arm64: dts: rockchip: rk3588-vehicle-evb: close dmc default media: i2c: rk628: fix get range when hdmirx detect default range ... Change-Id: I5cc37283e174e07d6ad42f4523ce4aa74845de8e
2026-06-05 02:21:52 +09:00 · 2025-04-28 20:43:25 +08:00
parent 72e7ce543c 559aa0ed87
commit 809e70e641
30 changed files with 314 additions and 135 deletions
--- a/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
+++ b/arch/arm/boot/dts/rk3036-evb1-ddr3-v10.dts
@@ -435,8 +435,8 @@
 					15 00 02 d2 32
 					15 00 02 d3 00
 					39 00 04 ff 98 81 00
-					05 00 01 11
-					05 01 01 29
+					05 96 01 11
+					05 14 01 29
 				];
 			};
 		};
--- a/arch/arm/boot/dts/rk3506b-test2-v10.dts
+++ b/arch/arm/boot/dts/rk3506b-test2-v10.dts
@@ -433,8 +433,8 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
-			05 01 01 29
+			05 96 01 11
+			05 14 01 29
 		];

 		disp_timings0: display-timings {
--- a/arch/arm/boot/dts/rv1126-evb-v10.dtsi
+++ b/arch/arm/boot/dts/rv1126-evb-v10.dtsi
@@ -430,8 +430,8 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
-			05 01 01 29
+			05 96 01 11
+			05 14 01 29
 		];

 		display-timings {
--- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v10.dts
@@ -293,6 +293,14 @@
 	};
 };

+&dfi {
+	status = "disabled";
+};
+
+&dmc {
+	status = "disabled";
+};
+
 &gmac1 {
 	status = "disabled";
 };
--- a/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dts
@@ -416,6 +416,14 @@
 	};
 };

+&dfi {
+	status = "disabled";
+};
+
+&dmc {
+	status = "disabled";
+};
+
 &gmac1 {
 	status = "disabled";
 };
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
@@ -330,6 +330,14 @@
 	};
 };

+&dfi {
+	status = "disabled";
+};
+
+&dmc {
+	status = "disabled";
+};
+
 &max96712_dphy3_vcc1v2 {
 	vin-supply = <&vcc5v0_buck>;
 };
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v23.dts
@@ -517,6 +517,14 @@
 	};
 };

+&dfi {
+	status = "disabled";
+};
+
+&dmc {
+	status = "disabled";
+};
+
 &gmac0 {
 	/* Use rgmii-rxid mode to disable rx delay inside Soc */
 	phy-mode = "rgmii-rxid";
--- a/arch/arm64/boot/dts/rockchip/rv1126bp-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126bp-evb.dtsi
@@ -305,8 +305,8 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
-			05 01 01 29
+			05 96 01 11
+			05 14 01 29
 		];

 		display-timings {
--- a/drivers/clk/rockchip/clk-rv1126b.c
+++ b/drivers/clk/rockchip/clk-rv1126b.c
@@ -866,10 +866,10 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
 	COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0,
 			RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS,
 			RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS),
-	GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_bus_root", 0,
-			RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS),
 	GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0,
 			RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS),
+	GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_rkrng_s_ns", 0,
+			RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS),
 	GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
 			RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS),
 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0,
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -327,10 +327,28 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,

 	/* Enable or disable dbclk at last */
 	if (div_debounce_support) {
-		if (debounce)
-			clk_prepare_enable(bank->db_clk);
-		else
-			clk_disable_unprepare(bank->db_clk);
+		raw_spin_lock_irqsave(&bank->slock, flags);
+
+		if (debounce) {
+			if (bitmap_empty(bank->db_clk_bitmap, RK_GPIO_BANK_MAX_PIN)) {
+				int ret = clk_enable(bank->db_clk);
+
+				if (ret)
+					dev_warn(bank->dev, "Failed to enable db_clk: %d\n", ret);
+				else
+					set_bit(offset, bank->db_clk_bitmap);
+			} else {
+				set_bit(offset, bank->db_clk_bitmap);
+			}
+		} else {
+			if (!bitmap_empty(bank->db_clk_bitmap, RK_GPIO_BANK_MAX_PIN)) {
+				clear_bit(offset, bank->db_clk_bitmap);
+				if (bitmap_empty(bank->db_clk_bitmap, RK_GPIO_BANK_MAX_PIN))
+					clk_disable(bank->db_clk);
+			}
+		}
+
+		raw_spin_unlock_irqrestore(&bank->slock, flags);
 	} else {
 		return -EOPNOTSUPP;
 	}
@@ -1140,8 +1158,16 @@ static int rockchip_gpio_probe(struct platform_device *pdev)
 		}
 	}

-	clk_prepare_enable(bank->clk);
-	clk_prepare_enable(bank->db_clk);
+	ret = clk_prepare_enable(bank->clk);
+	if (ret) {
+		dev_err(bank->dev, "Failed to enable GPIO clock: %d\n", ret);
+		return ret;
+	}
+	ret = clk_prepare(bank->db_clk);
+	if (ret) {
+		dev_warn(bank->dev, "Failed to prepare db_clk: %d\n", ret);
+		bank->db_clk = NULL;
+	}

 	ret = rockchip_gpio_parse_irqs(pdev, bank);
 	if (ret < 0)
@@ -1220,7 +1246,7 @@ err_unlock:
 	mutex_unlock(&bank->deferred_lock);
 err_clk:
 	clk_disable_unprepare(bank->clk);
-	clk_disable_unprepare(bank->db_clk);
+	clk_unprepare(bank->db_clk);

 	return ret;
 }
@@ -1241,7 +1267,10 @@ static int rockchip_gpio_remove(struct platform_device *pdev)
 	rockchip_gpio_remove_cpuhp();

 	clk_disable_unprepare(bank->clk);
-	clk_disable_unprepare(bank->db_clk);
+	if (bitmap_empty(bank->db_clk_bitmap, RK_GPIO_BANK_MAX_PIN))
+		clk_unprepare(bank->db_clk);
+	else
+		clk_disable_unprepare(bank->db_clk);
 	gpiochip_remove(&bank->gpio_chip);

 	return 0;
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -12896,6 +12896,8 @@ static void vop3_post_csc_config(struct drm_crtc *crtc, struct post_acm *acm, st

 	if (!vcstate->yuv_overlay || vp->has_dci_enabled_win)
 		convert_mode.is_input_full_range = true;
+	else if (vcstate->yuv_overlay)
+		convert_mode.is_input_full_range = false;
 	else if (has_yuv_plane)
 		convert_mode.is_input_full_range =
 			pstate->color_range == DRM_COLOR_YCBCR_FULL_RANGE ? 1 : 0;
--- a/drivers/media/i2c/rk628/rk628_csi_v4l2.c
+++ b/drivers/media/i2c/rk628/rk628_csi_v4l2.c
@@ -186,22 +186,22 @@ static u8 edid_init_data[] = {
 	0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
 	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x18,

-	0x02, 0x03, 0x1A, 0x71, 0x47, 0x5F, 0x90, 0x22,
+	0x02, 0x03, 0x1D, 0x71, 0x47, 0x5F, 0x90, 0x22,
 	0x04, 0x11, 0x02, 0x01, 0x23, 0x09, 0x07, 0x01,
 	0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
-	0x10, 0x00, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38,
-	0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0x20, 0xC2,
-	0x31, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72,
-	0x51, 0xD0, 0x1E, 0x20, 0x6E, 0x28, 0x55, 0x00,
-	0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x02, 0x3A,
-	0x80, 0xD0, 0x72, 0x38, 0x2D, 0x40, 0x10, 0x2C,
-	0x45, 0x80, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
-	0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
-	0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C, 0x00, 0x00,
-	0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C,
-	0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC0, 0x6C,
-	0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC1,
+	0x10, 0x00, 0xE2, 0x00, 0xCB, 0x02, 0x3A, 0x80,
+	0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45,
+	0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x01,
+	0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E,
+	0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00,
+	0x1E, 0x02, 0x3A, 0x80, 0xD0, 0x72, 0x38, 0x2D,
+	0x40, 0x10, 0x2C, 0x45, 0x80, 0x20, 0xC2, 0x31,
+	0x00, 0x00, 0x1E, 0x01, 0x1D, 0x80, 0x18, 0x71,
+	0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xC0,
+	0x6C, 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80,
+	0x18, 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25,
+	0x00, 0xC0, 0x6C, 0x00, 0x00, 0x00, 0x18, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
 };

 static u8 rk628f_edid_init_data[] = {
@@ -222,22 +222,22 @@ static u8 rk628f_edid_init_data[] = {
 	0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
 	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA8,

-	0x02, 0x03, 0x39, 0xF2, 0x4D, 0x01, 0x03, 0x12,
+	0x02, 0x03, 0x3C, 0xF2, 0x4D, 0x01, 0x03, 0x12,
 	0x13, 0x84, 0x22, 0x1F, 0x90, 0x5D, 0x5E, 0x5F,
 	0x60, 0x61, 0x23, 0x09, 0x07, 0x07, 0x83, 0x01,
 	0x00, 0x00, 0x6D, 0x03, 0x0C, 0x00, 0x10, 0x00,
 	0x00, 0x44, 0x20, 0x00, 0x60, 0x03, 0x02, 0x01,
 	0x67, 0xD8, 0x5D, 0xC4, 0x01, 0x78, 0x80, 0x00,
 	0xE3, 0x05, 0x03, 0x01, 0xE4, 0x0F, 0x00, 0x18,
-	0x00, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D,
-	0x40, 0x58, 0x2C, 0x45, 0x00, 0xB9, 0xA8, 0x42,
-	0x00, 0x00, 0x1E, 0x08, 0xE8, 0x00, 0x30, 0xF2,
-	0x70, 0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0xC4,
-	0x8E, 0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00,
+	0x00, 0xE2, 0x00, 0xCB, 0x02, 0x3A, 0x80, 0x18,
+	0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00,
+	0xB9, 0xA8, 0x42, 0x00, 0x00, 0x1E, 0x08, 0xE8,
+	0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
+	0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD3,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
 };


@@ -956,7 +956,8 @@ static void enable_stream(struct v4l2_subdev *sd, bool en)
 			enable_csitx(sd);

 		rk628_hdmirx_vid_enable(sd, true);
-		if (csi->plat_data->tx_mode == CSI_MODE) {
+		if (csi->plat_data->tx_mode == CSI_MODE &&
+		    csi->rk628->version >= RK628F_VERSION) {
 			msleep(20);
 			rk628_mipi_txdata_reset(sd);
 			rk628_csi_enable_csi_interrupts(sd, true);
@@ -968,8 +969,10 @@ static void enable_stream(struct v4l2_subdev *sd, bool en)
 				      GCPFORCE_CLRAVMUTE_MASK, GCPFORCE_CLRAVMUTE(0));
 	} else {
 		if (csi->plat_data->tx_mode == CSI_MODE) {
-			rk628_csi_enable_csi_interrupts(sd, false);
-			msleep(20);
+			if (csi->rk628->version >= RK628F_VERSION) {
+				rk628_csi_enable_csi_interrupts(sd, false);
+				msleep(20);
+			}
 			rk628_hdmirx_vid_enable(sd, false);
 			rk628_csi_disable_stream(sd);
 		} else {
--- a/drivers/media/i2c/rk628/rk628_hdmirx.c
+++ b/drivers/media/i2c/rk628/rk628_hdmirx.c
@@ -1857,6 +1857,7 @@ u8 rk628_hdmirx_get_range(struct rk628 *rk628)
 {
 	u8 color_range, yuv_range;
 	u32 val, vic, fmt, avi_hb;
+	bool dvi;

 	rk628_i2c_read(rk628, HDMI_RX_PDEC_AVI_PB, &val);
 	rk628_i2c_read(rk628, HDMI_RX_PDEC_AVI_HB, &avi_hb);
@@ -1864,6 +1865,8 @@ u8 rk628_hdmirx_get_range(struct rk628 *rk628)
 	yuv_range = (avi_hb & YUV_COLORRANGE_MASK) >> 30;
 	vic = (val & VID_IDENT_CODE_MASK) >> 24;
 	fmt = (val & VIDEO_FORMAT_MASK) >> 5;
+	rk628_i2c_read(rk628, HDMI_RX_PDEC_STS, &val);
+	dvi = !!(val & DVI_DET);
 	if (fmt != HDMIRX_RGB888) {
 		if (yuv_range == HDMIRX_YCC_LIMIT)
 			color_range = HDMIRX_LIMIT_RANGE;
@@ -1871,11 +1874,13 @@ u8 rk628_hdmirx_get_range(struct rk628 *rk628)
 			color_range = HDMIRX_FULL_RANGE;
 		else
 			color_range = HDMIRX_DEFAULT_RANGE;
-	}
-	if (fmt == HDMIRX_RGB888 && color_range == HDMIRX_DEFAULT_RANGE) {
-		(vic) ?
-		(color_range = HDMIRX_LIMIT_RANGE) :
-		(color_range = HDMIRX_FULL_RANGE);
+	} else {
+		if (dvi)
+			color_range = HDMIRX_FULL_RANGE;
+		if (color_range == HDMIRX_DEFAULT_RANGE)
+			vic ?
+			(color_range = HDMIRX_FULL_RANGE) :
+			(color_range = HDMIRX_LIMIT_RANGE);
 	}

 	return color_range;
--- a/drivers/media/platform/rockchip/cif/capture.c
+++ b/drivers/media/platform/rockchip/cif/capture.c
@@ -1011,13 +1011,10 @@ cif_input_fmt *rkcif_get_input_fmt(struct rkcif_device *dev, struct v4l2_rect *r
 			csi_info->vc = ch_info.vc;
 		else
 			csi_info->vc = pad_id;
-		if (ch_info.bus_fmt == MEDIA_BUS_FMT_SPD_2X8 ||
-		    ch_info.bus_fmt == MEDIA_BUS_FMT_EBD_1X8) {
-			if (ch_info.data_type > 0)
-				csi_info->data_type = ch_info.data_type;
-			if (ch_info.data_bit > 0)
-				csi_info->data_bit = ch_info.data_bit;
-		}
+		if (ch_info.data_type > 0)
+			csi_info->data_type = ch_info.data_type;
+		if (ch_info.data_bit > 0)
+			csi_info->data_bit = ch_info.data_bit;
 		if (ch_info.field == 0)
 			fmt.format.field = V4L2_FIELD_NONE;
 		else
@@ -4059,19 +4056,13 @@ static int rkcif_csi_channel_init(struct rkcif_stream *stream,
 		channel->virtual_width *= 2;
 		channel->height /= 2;
 	}
-	if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
-	    stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
-		if (dev->channels[stream->id].data_type)
-			channel->data_type = dev->channels[stream->id].data_type;
-		else
-			channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
-							   channel->cmd_mode_en,
-							   channel->dsi_input);
-	} else {
+	if (dev->channels[stream->id].data_type)
+		channel->data_type = dev->channels[stream->id].data_type;
+	else
 		channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
 						   channel->cmd_mode_en,
 						   channel->dsi_input);
-	}
+
 	channel->csi_fmt_val = get_csi_fmt_val(stream,
 					       &dev->channels[stream->id]);

--- a/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
+++ b/drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
@@ -322,58 +322,58 @@ static u8 edid_init_data_340M[] = {
 	0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
 	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7,

-	0x02, 0x03, 0x2E, 0xF1, 0x51, 0x07, 0x16, 0x14,
+	0x02, 0x03, 0x31, 0xF1, 0x51, 0x07, 0x16, 0x14,
 	0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
 	0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
 	0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
 	0x0C, 0x00, 0x30, 0x00, 0x00, 0x44, 0xE3, 0x05,
-	0x03, 0x01, 0xE3, 0x0E, 0x60, 0x61, 0x02, 0x3A,
-	0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
-	0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
+	0x03, 0x01, 0xE3, 0x0E, 0x60, 0x61, 0xE2, 0x00,
+	0xCB, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D,
+	0x40, 0x58, 0x2C, 0x45, 0x00, 0x20, 0xC2, 0x31,
+	0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD2,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22,
 };

 static u8 edid_init_data_600M[] = {
 	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
-	0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
+	0x24, 0xD0, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
+	0x2D, 0x20, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
 	0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
-	0x09, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40,
+	0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0,
 	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, 0xE8,
 	0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
 	0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
-	0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80,
-	0xB0, 0x58, 0x8A, 0x00, 0x20, 0xC2, 0x31, 0x00,
-	0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
-	0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
-	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
+	0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
+	0x58, 0x2C, 0x45, 0x00, 0xB9, 0xA8, 0x42, 0x00,
+	0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x49,
+	0x46, 0x50, 0x20, 0x44, 0x69, 0x73, 0x70, 0x6C,
+	0x61, 0x79, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
 	0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
-	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x39,
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xDD,

-	0x02, 0x03, 0x22, 0xF2, 0x41, 0x61, 0x23, 0x09,
-	0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
-	0x0C, 0x00, 0x30, 0x00, 0x00, 0x78, 0x67, 0xD8,
-	0x5D, 0xC4, 0x01, 0x78, 0xC0, 0x00, 0xE3, 0x05,
-	0x03, 0x01, 0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70,
-	0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0xC4, 0x8E,
-	0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00,
+	0x02, 0x03, 0x40, 0xF2, 0x51, 0x07, 0x16, 0x14,
+	0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
+	0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
+	0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x6D, 0x03,
+	0x0C, 0x00, 0x10, 0x00, 0x00, 0x44, 0x20, 0x00,
+	0x60, 0x03, 0x02, 0x01, 0x67, 0xD8, 0x5D, 0xC4,
+	0x01, 0x78, 0xC0, 0x00, 0xE3, 0x05, 0x03, 0x01,
+	0xE4, 0x0F, 0x00, 0x80, 0x01, 0xE2, 0x00, 0xCB,
+	0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80,
+	0xB0, 0x58, 0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00,
+	0x00, 0x1E, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38,
+	0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xB9, 0xA8,
+	0x42, 0x00, 0x00, 0x9E, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBC,
 };

 static char *hdmirx_color_space[8] = {
@@ -4328,6 +4328,7 @@ static const struct hdmirx_reg_table hdmirx_ctrl_table[] = {
 	{0x7c0, 0x7c8, HDMIRX_ATTR_RW},
 	{0x7cc, 0x7d0, HDMIRX_ATTR_RO},
 	{0x7d4, 0x7d4, HDMIRX_ATTR_RW},
+	{0x1200, 0x125c, HDMIRX_ATTR_RO},
 	{0x1580, 0x1598, HDMIRX_ATTR_RO},
 	{0x2000, 0x2000, HDMIRX_ATTR_WO},
 	{0x2004, 0x2004, HDMIRX_ATTR_RO},
--- a/drivers/media/platform/rockchip/isp/csi.c
+++ b/drivers/media/platform/rockchip/isp/csi.c
@@ -497,6 +497,7 @@ int rkisp_csi_get_hdr_cfg(struct rkisp_device *dev, void *arg)
 	struct rkmodule_hdr_cfg *cfg = arg;
 	struct v4l2_subdev *sd = NULL;
 	u32 type;
+	int ret;

 	if (dev->isp_inp & INP_CSI) {
 		type = MEDIA_ENT_F_CAM_SENSOR;
@@ -521,7 +522,13 @@ int rkisp_csi_get_hdr_cfg(struct rkisp_device *dev, void *arg)
 		return -EINVAL;
 	}

-	return v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_HDR_CFG, cfg);
+	ret = v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_HDR_CFG, cfg);
+	if (ret == -ENOIOCTLCMD) {
+		cfg->esp.mode = HDR_NORMAL_VC;
+		cfg->hdr_mode = NO_HDR;
+		ret = 0;
+	}
+	return ret;
 }

 int rkisp_csi_config_patch(struct rkisp_device *dev, bool is_pre_cfg)
--- a/drivers/media/platform/rockchip/isp/isp_params_v35.c
+++ b/drivers/media/platform/rockchip/isp/isp_params_v35.c
@@ -347,7 +347,7 @@ isp_bls_config(struct rkisp_isp_params_vdev *params_vdev,
 	}

 	new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id);
-	new_control &= (ISP_BLS_ENA | ISP32_BLS_BLS2_EN);
+	new_control &= (ISP_BLS_ENA | ISP32_BLS_BLS2_EN | ISP35_BLS_BLS3_EN);
 	if (arg->bls1_en)
 		new_control |= ISP_BLS_BLS1_EN;

@@ -2205,7 +2205,7 @@ isp_aiawb_config(struct rkisp_isp_params_vdev *params_vdev,
 	value = ISP_PACK_2SHORT(arg->mr00, arg->mr01);
 	isp3_param_write(params_vdev, value, ISP35_AIAWB_MATRIX_ROT0, id);
 	value = ISP_PACK_2SHORT(arg->mr10, arg->mr11);
-	isp3_param_write(params_vdev, value, ISP35_AIAWB_MATRIX_ROT0, id);
+	isp3_param_write(params_vdev, value, ISP35_AIAWB_MATRIX_ROT1, id);
 }

 static void
--- a/drivers/media/platform/rockchip/vpss/procfs.c
+++ b/drivers/media/platform/rockchip/vpss/procfs.c
@@ -25,14 +25,17 @@ static void show_hw(struct seq_file *p, struct rkvpss_hw_dev *hw)
 	}

 	seq_printf(p, "\n%s\n", "HW INFO");
+
 	val = rkvpss_hw_read(hw, RKVPSS_VPSS_CTRL);
-	seq_printf(p, "\tmirror:%s(0x%x)\n", (val & 0x10) ? "ON" : "OFF", val);
+	seq_printf(p, "\tmirror:%s(0x%x)\n", (val & RKVPSS_MIR_EN) ? "ON" : "OFF", val);
+	val = rkvpss_hw_read(hw, RKVPSS_VPSS_ONLINE);
+	seq_printf(p, "\tcmsc:%s(0x%x)\n", (val & RKVPSS_ISP2VPSS_ONLINE2_CMSC_EN) ? "ON" : "OFF", val);

 	for (i = 0; i < vpss_outchn_max(hw->vpss_ver); i++) {
 		seq_printf(p, "\toutput[%d]", i);
-		val = rkvpss_hw_read(hw, RKVPSS_CMSC_CTRL);
-		mask = RKVPSS_CMSC_CHN_EN(i);
-		seq_printf(p, "\tcmsc:%s(0x%x)", (val & mask & 1) ? "ON" : "OFF", val);
+		val = rkvpss_hw_read(hw, RKVPSS_VPSS_ONLINE);
+		mask = (RKVPSS_ISP2VPSS_CHN0_SEL(3) << i * 2);
+		seq_printf(p, "\tchn_sel:%s(0x%x)", (val & mask) ? "ON" : "OFF", val);
 		if (hw->is_ofl_ch[i]) {
 			val = rkvpss_hw_read(hw, RKVPSS_CROP0_CTRL);
 			mask = RKVPSS_CROP_CHN_EN(i);
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -183,6 +183,7 @@
 #define RK_GPIO4_D6	158
 #define RK_GPIO4_D7	159

+#define RK_GPIO_BANK_MAX_PIN		32
 #define RK_GPIO_IRQ_MAX_NUM		4
 #define RK_GPIO_EXP_IRQ_MAX_PIN_NUM	2

@@ -335,6 +336,7 @@ struct rockchip_pin_bank {
 	struct regmap			*regmap_pull;
 	struct clk			*clk;
 	struct clk			*db_clk;
+	unsigned long			db_clk_bitmap[BITS_TO_LONGS(RK_GPIO_BANK_MAX_PIN)];
 	int				irq[RK_GPIO_IRQ_MAX_NUM];
 	u32				irq_pins[RK_GPIO_IRQ_MAX_NUM];
 	int				irq_pin_id[RK_GPIO_IRQ_MAX_NUM][RK_GPIO_EXP_IRQ_MAX_PIN_NUM];
--- a/drivers/pwm/pwm-rockchip-test.c
+++ b/drivers/pwm/pwm-rockchip-test.c
@@ -18,10 +18,11 @@
 #define PWM_CONTROLLER_NUM_MAX	4
 #define PWM_CHANNEL_NUM_MAX	8

-#define PWM_WAVE_8BIT_TEST 1
+#define PWM_WAVE_BREATHING_LIGHT_8BIT_TEST 1

 /* 400k pwm_dclk src */
-#ifdef PWM_WAVE_8BIT_TEST
+#ifndef PWM_WAVE_PRIOD_DUTY_BOTH_UPDATE_TEST
+#ifdef PWM_WAVE_BREATHING_LIGHT_8BIT_TEST
 #define PWM_TABLE_MAX		256
 #define PWM_WIDTH_MODE		PWM_WAVE_TABLE_8BITS_WIDTH
 /* in nanoseconds */
@@ -34,6 +35,7 @@
 #define PWM_WAVE_STEP		10000
 #define PWM_WAVE_RPT		10
 #endif
+#endif

 struct pwm_test_data {
 	struct pwm_device *pwm_dev;
@@ -156,8 +158,12 @@ static void pwm_rockchip_test_help_info(void)
 	pr_info("\n");
 	pr_info("wave generator demo:\n");
 	pr_info("echo wave 0 1 true > /dev/pwm_rockchip_misc_test\n");
+	pr_info("[brathing light demo with 8bit table]\n");
 	pr_info("echo continuous 0 1 640000 320000 normal > /dev/pwm_rockchip_misc_test\n");
+	pr_info("[brathing light demo with 16bit table]\n");
 	pr_info("echo continuous 0 1 1000000 500000 normal > /dev/pwm_rockchip_misc_test\n");
+	pr_info("[demo for updating both period and duty]\n");
+	pr_info("echo continuous 0 1 1000 500 normal > /dev/pwm_rockchip_misc_test\n");
 	pr_info("echo enable 0 1 true > /dev/pwm_rockchip_misc_test\n");
 	pr_info("------------------------------------------------------------------------------------\n");
 }
@@ -200,7 +206,7 @@ static ssize_t pwm_rockchip_test_write(struct file *file, const char __user *buf
 	struct pwm_device *pdev;
 	struct pwm_state state;
 	struct pwm_capture cap_res;
-	struct rockchip_pwm_wave_table duty_table;
+	struct rockchip_pwm_wave_table wave_table;
 	struct rockchip_pwm_wave_config wave_config;
 	struct rockchip_pwm_biphasic_config biphasic_config;
 	enum rockchip_pwm_freq_meter_input_sel freq_input_sel;
@@ -627,14 +633,59 @@ static ssize_t pwm_rockchip_test_write(struct file *file, const char __user *buf
 			goto exit;
 		}

+#ifdef PWM_WAVE_PRIOD_DUTY_BOTH_UPDATE_TEST
+		/*
+		 * The output wave should be like:
+		 *    _   _   _   _   _
+		 *   | | | | | | | | | |
+		 * __| |_| |_| |_| |_| |_____________________________________
+		 *
+		 * |                   |                                    |
+		 * |  five 400K waves  |             delay 10ms             |
+		 * |                   |                                    |
+		 */
+		table[0] = 2500;
+		table[1] = 500000; // avoid exceeding the 16-bit table
+		table[2] = 500000;
+		table[3] = 500000;
+		table[4] = 500000;
+		table[5] = 1250;
+		table[6] = 0;
+		table[7] = 0;
+		table[8] = 0;
+		table[9] = 0;
+
+		wave_table.table = table;
+		wave_table.offset = 0;
+		wave_table.len = 10;
+
+		wave_config.wave_table = &wave_table;
+		wave_config.clk_src = PWM_SELECT_CLK_PWM;
+		wave_config.mem_clk_src = PWM_SELECT_CLK_PWM_OSC;
+		wave_config.width_mode = PWM_WAVE_TABLE_16BITS_WIDTH;
+		wave_config.update_mode = PWM_WAVE_INCREASING;
+		wave_config.enable = enable;
+		wave_config.duty_en = true;
+		wave_config.period_en = true;
+		wave_config.clk_rate = 100000000;
+		wave_config.rpt = 4;
+		wave_config.duty_max = 9;
+		wave_config.duty_min = 5;
+		wave_config.period_max = 4;
+		wave_config.period_min = 0;
+		wave_config.offset = 0;
+		wave_config.middle = 0;
+		wave_config.max_hold = 0;
+		wave_config.min_hold = 0;
+		wave_config.middle_hold = 0;
+#else
 		for (i = 0; i < PWM_TABLE_MAX; i++)
 			table[i] = i * PWM_WAVE_STEP;
-		duty_table.table = table;
-		duty_table.offset = (channel_id % 3) * PWM_TABLE_MAX;
-		duty_table.len = PWM_TABLE_MAX;
+		wave_table.table = table;
+		wave_table.offset = (channel_id % 3) * PWM_TABLE_MAX;
+		wave_table.len = PWM_TABLE_MAX;

-		wave_config.duty_table = &duty_table;
-		wave_config.period_table = NULL;
+		wave_config.wave_table = &wave_table;
 		wave_config.clk_src = PWM_SELECT_CLK_PWM;
 		wave_config.mem_clk_src = PWM_SELECT_CLK_PWM_OSC;
 		wave_config.width_mode = PWM_WIDTH_MODE;
@@ -653,6 +704,7 @@ static ssize_t pwm_rockchip_test_write(struct file *file, const char __user *buf
 		wave_config.max_hold = 3;
 		wave_config.min_hold = 0;
 		wave_config.middle_hold = 2;
+#endif

 		ret = rockchip_pwm_set_wave(pdev, &wave_config);
 		if (ret) {
@@ -662,8 +714,10 @@ static ssize_t pwm_rockchip_test_write(struct file *file, const char __user *buf
 			goto exit;
 		}

+#ifndef PWM_WAVE_PRIOD_DUTY_BOTH_UPDATE_TEST
 		pr_info("%s %s mode for pwm%d_%d: table_len = %d, table_step = %d\n",
 			argv[2], cmd, controller_id, channel_id, PWM_TABLE_MAX, PWM_WAVE_STEP);
+#endif
 		break;
 	case PWM_GLOBAL_CTRL:
 		if (!argv[0]) {
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -1676,18 +1676,8 @@ int rockchip_pwm_set_wave(struct pwm_device *pwm, struct rockchip_pwm_wave_confi
 		}
 	}

-	if (config->duty_table) {
-		ret = pc->data->funcs.set_wave_table(chip, pwm, config->duty_table,
-						     config->width_mode);
-		if (ret) {
-			dev_err(chip->dev, "Failed to set wave duty table for PWM%d\n",
-				pc->channel_id);
-			goto err_disable_clk_osc;
-		}
-	}
-
-	if (config->period_table) {
-		ret = pc->data->funcs.set_wave_table(chip, pwm, config->period_table,
+	if (config->wave_table) {
+		ret = pc->data->funcs.set_wave_table(chip, pwm, config->wave_table,
 						     config->width_mode);
 		if (ret) {
 			dev_err(chip->dev, "Failed to set wave period table for PWM%d\n",
--- a/drivers/rknpu/rknpu_drv.c
+++ b/drivers/rknpu/rknpu_drv.c
@@ -1451,6 +1451,7 @@ static int rknpu_probe(struct platform_device *pdev)
 	rknpu_dev->heap = rk_dma_heap_find("rk-dma-heap-cma");
 	if (!rknpu_dev->heap) {
 		LOG_DEV_ERROR(dev, "failed to find cma heap\n");
+		misc_deregister(&rknpu_dev->miscdev);
 		return -ENOMEM;
 	}
 	rk_dma_heap_set_dev(dev);
--- a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c
+++ b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.c
@@ -80,6 +80,7 @@ struct rkvdec_link_info rkvdec_link_v2_hw_info = {
 	.irq_base = 0x00,
 	.next_addr_base = 0x1c,
 	.err_mask = 0xf0,
+	.en_sw_iommu_zap = 1,
 };

 /* vdpu34x link hw info for rk356x */
@@ -142,6 +143,7 @@ struct rkvdec_link_info rkvdec_link_rk356x_hw_info = {
 	.irq_base = 0x00,
 	.next_addr_base = 0x1c,
 	.err_mask = 0xf0,
+	.en_sw_iommu_zap = 1,
 };

 /* vdpu382 link hw info */
@@ -204,6 +206,7 @@ struct rkvdec_link_info rkvdec_link_vdpu382_hw_info = {
 	.irq_base = 0x00,
 	.next_addr_base = 0x1c,
 	.err_mask = 0xf0,
+	.en_sw_iommu_zap = 1,
 };

 /* vdpu383 link hw info */
@@ -264,6 +267,7 @@ struct rkvdec_link_info rkvdec_link_vdpu383_hw_info = {
 	.en_base = 0x40,
 	.ip_en_base = 0x58,
 	.ip_en_val = 0x01000000,
+	.en_sw_iommu_zap = 1,
 };

 /* vdpu384a link hw info */
@@ -509,7 +513,9 @@ static int rkvdec2_link_enqueue(struct rkvdec_link_dev *link_dec,
 	/* start config before all registers are set */
 	wmb();

-	mpp_iommu_flush_tlb(link_dec->mpp->iommu_info);
+	/* After rv1126b, hw can execute zap. */
+	if (link_info->en_sw_iommu_zap)
+		mpp_iommu_flush_tlb(link_dec->mpp->iommu_info);
 	mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);

 	link_dec->task_running++;
--- a/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h
+++ b/drivers/video/rockchip/mpp/mpp_rkvdec2_link.h
@@ -137,6 +137,8 @@ struct rkvdec_link_info {
 	u32 en_base;
 	u32 ip_en_base;
 	u32 ip_en_val;
+
+	u32 en_sw_iommu_zap;
 };

 struct rkvdec_link_dev {
--- a/drivers/video/rockchip/rga3/rga_drv.c
+++ b/drivers/video/rockchip/rga3/rga_drv.c
@@ -395,8 +395,6 @@ int rga_power_enable(struct rga_scheduler_t *scheduler)
 	return 0;

 err_enable_clk:
-	clk_bulk_disable_unprepare(scheduler->num_clks, scheduler->clks);
-
 	pm_relax(scheduler->dev);
 	pm_runtime_put_sync_suspend(scheduler->dev);

--- a/drivers/video/rockchip/rga3/rga_hw_config.c
+++ b/drivers/video/rockchip/rga3/rga_hw_config.c
@@ -612,8 +612,8 @@ const struct rga_hw_data rga2e_1106_data = {

 const struct rga_hw_data rga2e_3506_data = {
 	.version = 0,
-	.input_range = {{2, 2}, {1280, 1280}},
-	.output_range = {{2, 2}, {1280, 1280}},
+	.input_range = {{2, 2}, {1280, 8192}},
+	.output_range = {{2, 2}, {1280, 4096}},

 	.win = rga2e_3506_win_data,
 	.win_size = ARRAY_SIZE(rga2e_3506_win_data),
@@ -688,8 +688,8 @@ const struct rga_hw_data rga2p_iommu_data = {

 const struct rga_hw_data rga2p_lite_1103b_data = {
 	.version = 0,
-	.input_range = {{2, 2}, {2880, 1620}},
-	.output_range = {{2, 2}, {2880, 1620}},
+	.input_range = {{2, 2}, {2880, 8192}},
+	.output_range = {{2, 2}, {2880, 8192}},

 	.win = rga2p_lite_win_data,
 	.win_size = ARRAY_SIZE(rga2p_lite_win_data),
--- a/drivers/video/rockchip/vehicle/vehicle_generic_sensor.c
+++ b/drivers/video/rockchip/vehicle/vehicle_generic_sensor.c
@@ -210,7 +210,7 @@ int vehicle_generic_sensor_read(struct vehicle_ad_dev *ad, char reg)
 //	msgs[1].scl_rate = ad->i2c_rate;

 	ret = i2c_transfer(ad->adapter, msgs, 2);
-	if (ret)
+	if (ret < 0)
 		return ret;

 	return pval;
--- a/include/linux/pwm-rockchip.h
+++ b/include/linux/pwm-rockchip.h
@@ -99,8 +99,7 @@ enum rockchip_pwm_wave_update_mode {

 /**
 * struct rockchip_pwm_wave_config - wave generator config object
- * @duty_table: the wave table config of duty
- * @period_table: the wave table config of period
+ * @wave_table: the wave table config
 * @clk_src: the clk src selection in wave generator mode
 * @mem_clk_src: the memory clk src selection in wave generator mode
 * @width_mode: the width mode of wave table
@@ -121,8 +120,7 @@ enum rockchip_pwm_wave_update_mode {
 * @middle_hold: the time to stop at middle address
 */
 struct rockchip_pwm_wave_config {
-	struct rockchip_pwm_wave_table *duty_table;
-	struct rockchip_pwm_wave_table *period_table;
+	struct rockchip_pwm_wave_table *wave_table;
 	enum rockchip_pwm_clk_src_sel clk_src;
 	enum rockchip_pwm_clk_src_sel mem_clk_src;
 	enum rockchip_pwm_wave_table_width_mode width_mode;
--- a/include/uapi/linux/rk-camera-module.h
+++ b/include/uapi/linux/rk-camera-module.h
@@ -204,6 +204,15 @@
 #define RKMODULE_GET_EXP_INFO       \
 	_IOR('V', BASE_VIDIOC_PRIVATE + 46, struct rkmodule_exp_info)

+#define RKMODULE_SET_WB_GAIN  \
+	_IOW('V', BASE_VIDIOC_PRIVATE + 47, struct rkmodule_wb_gain_group)
+
+#define RKMODULE_SET_BLC  \
+	_IOW('V', BASE_VIDIOC_PRIVATE + 48, struct rkmodule_blc_group)
+
+#define RKMODULE_GET_SPD_RATIO	\
+	_IOR('V', BASE_VIDIOC_PRIVATE + 49, struct rkmodule_dcg_ratio)
+
 struct rkmodule_i2cdev_info {
 	__u8 slave_addr;
 } __attribute__ ((packed));
@@ -895,4 +904,41 @@ struct rkmodule_exp_info {
 	__u32 reserved[6];
 } __attribute__ ((packed));

+#define RKMODULE_MAX_WB_GAIN_GROUP (4)
+
+enum rkmodule_wb_type {
+	RKMODULE_HCG_WB_GAIN,
+	RKMODULE_LCG_WB_GAIN,
+	RKMODULE_SPD_WB_GAIN,
+	RKMODULE_VS_WB_GAIN,
+};
+
+struct rkmodule_wb_gain {
+	__u32 b_gain;
+	__u32 gb_gain;
+	__u32 gr_gain;
+	__u32 r_gain;
+};
+
+struct rkmodule_wb_gain_group {
+	__u32 group_num;
+	enum rkmodule_wb_type wb_gain_type[RKMODULE_MAX_WB_GAIN_GROUP];
+	struct rkmodule_wb_gain wb_gain[RKMODULE_MAX_WB_GAIN_GROUP];
+};
+
+#define RKMODULE_MAX_BLC_GROUP (4)
+
+enum rkmodule_blc_type {
+	RKMODULE_HCG_BLC,
+	RKMODULE_LCG_BLC,
+	RKMODULE_SPD_BLC,
+	RKMODULE_VS_BLC,
+};
+
+struct rkmodule_blc_group {
+	__u32 group_num;
+	enum rkmodule_blc_type blc_type[RKMODULE_MAX_BLC_GROUP];
+	__u32 blc[RKMODULE_MAX_BLC_GROUP];
+};
+
 #endif /* _UAPI_RKMODULE_CAMERA_H */
--- a/sound/soc/codecs/rk_dsm.c
+++ b/sound/soc/codecs/rk_dsm.c
@@ -380,9 +380,9 @@ static int rk_dsm_hw_params(struct snd_pcm_substream *substream,
 		snd_soc_component_get_drvdata(dai->component);
 	unsigned int srt = 0, val = 0;

-	rk_dsm_set_clk(rd, substream, params_rate(params));
-
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		rk_dsm_set_clk(rd, substream, params_rate(params));
+
 		switch (params_rate(params)) {
 		case 8000:
 		case 11025:
@@ -460,6 +460,9 @@ static int rk_dsm_pcm_startup(struct snd_pcm_substream *substream,
 	struct rk_dsm_priv *rd =
 		snd_soc_component_get_drvdata(dai->component);

+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+		return 0;
+
 	/* Recover DAC Volumes */
 	regmap_write(rd->regmap, DACVOLL0, rd->vols.vol_l);
 	regmap_write(rd->regmap, DACVOLR0, rd->vols.vol_r);
@@ -489,6 +492,9 @@ static void rk_dsm_pcm_shutdown(struct snd_pcm_substream *substream,
 	struct rk_dsm_priv *rd =
 		snd_soc_component_get_drvdata(dai->component);

+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+		return;
+
 	gpiod_set_value(rd->pa_ctl, 0);

 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
@@ -519,6 +525,9 @@ static int rk_dsm_pcm_trigger(struct snd_pcm_substream *substream,
 	struct rk_dsm_priv *rd =
 		snd_soc_component_get_drvdata(dai->component);

+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+		return 0;
+
 	switch (cmd) {
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_RESUME: