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tvafe: adc pll FRQ can't over 4.8Ghz [1/1]

Browse Source 
PD#SWPL-12753, PD#TV-8736

Problem:
ft had change the Max range to 4.8G, so adc pll can't
over than 4.8 Ghz.

Solution:
modify pll default setting

Verify:
tl1

Change-Id: I9f489300762f653f967e8c2219c79882236062ab
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-08-15 10:35:09 +08:00
parent b7732f1dc5
commit 80b2c12a60
1 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c
View File

@@ -699,15 +699,15 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
mutex_lock(&pll_mutex);
if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
do {
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL1_TL1, 0x05400000);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x01200490);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x31200490);
W_HIU_REG(HHI_ADC_PLL_CNTL1_TL1, 0x06c00000);
W_HIU_REG(HHI_ADC_PLL_CNTL2_TL1, 0xe1800000);
W_HIU_REG(HHI_ADC_PLL_CNTL3_TL1, 0x48681c00);
W_HIU_REG(HHI_ADC_PLL_CNTL4_TL1, 0x88770290);
W_HIU_REG(HHI_ADC_PLL_CNTL5_TL1, 0x39272000);
W_HIU_REG(HHI_ADC_PLL_CNTL6_TL1, 0x56540000);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x111104e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x11010490);
udelay(100);
adc_pll_lock_cnt++;
@@ -762,15 +762,15 @@ int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara)
mutex_lock(&pll_mutex);
if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
do {
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL1_TL1, 0x05400000);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x01200490);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x31200490);
W_HIU_REG(HHI_ADC_PLL_CNTL1_TL1, 0x06c00000);
W_HIU_REG(HHI_ADC_PLL_CNTL2_TL1, 0xe0800000);
W_HIU_REG(HHI_ADC_PLL_CNTL3_TL1, 0x48681c00);
W_HIU_REG(HHI_ADC_PLL_CNTL4_TL1, 0x88770290);
W_HIU_REG(HHI_ADC_PLL_CNTL5_TL1, 0x39272000);
W_HIU_REG(HHI_ADC_PLL_CNTL6_TL1, 0x56540000);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x111104e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x11010490);
udelay(100);
adc_pll_lock_cnt++;