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hdmirx: update config for TM2 [1/1]

Browse Source 
PD#SWPL-5616

Problem:
bring up hdmirx for TM2

Solution:
hdmirx: add hdmirx TM2 support

Verify:
Verfied on TM2 skt board

Change-Id: I82fd66afc7f26f1bdfd7a4f1fc4cc0d9d7ed3974
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
This commit is contained in:
Lei Yang
2019-04-02 14:36:33 +08:00
committed by Jianxiong Pan
parent eea311172d
commit 80d7a1ae75
16 changed files with 79 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -550,7 +550,7 @@
};
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -805,7 +805,7 @@
};
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -777,7 +777,7 @@
}; /* End unifykey */
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -806,7 +806,7 @@
};
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -778,7 +778,7 @@
}; /* End unifykey */
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm64/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -550,7 +550,7 @@
};
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -800,7 +800,7 @@
};
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -776,7 +776,7 @@
}; /* End unifykey */
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -786,7 +786,7 @@
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

2
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -777,7 +777,7 @@
}; /* End unifykey */
hdmirx {
compatible = "amlogic, hdmirx_tl1";
compatible = "amlogic, hdmirx_tm2";
#address-cells=<1>;
#size-cells=<1>;
memory-region = <&hdmirx_emp_cma_reserved>;

15
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
View File

@@ -158,6 +158,11 @@ static struct notifier_block aml_hdcp22_pm_notifier = {
.notifier_call = aml_hdcp22_pm_notify,
};
static struct meson_hdmirx_data rx_tm2_data = {
.chip_id = CHIP_ID_TM2,
.phy_ver = PHY_VER_TL1,
};
static struct meson_hdmirx_data rx_tl1_data = {
.chip_id = CHIP_ID_TL1,
.phy_ver = PHY_VER_TL1,
@@ -184,6 +189,10 @@ static struct meson_hdmirx_data rx_gxtvbb_data = {
};
static const struct of_device_id hdmirx_dt_match[] = {
{
.compatible = "amlogic, hdmirx_tm2",
.data = &rx_tm2_data
},
{
.compatible = "amlogic, hdmirx_tl1",
.data = &rx_tl1_data
@@ -1747,7 +1756,7 @@ static void rx_phy_resume(void)
void rx_emp_resource_allocate(struct device *dev)
{
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* allocate buffer */
if (!rx.empbuff.storeA)
rx.empbuff.storeA =
@@ -1792,7 +1801,7 @@ void rx_tmds_resource_allocate(struct device *dev)
/*phys_addr_t p_addr;*/
/*struct page *pg_addr;*/
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
if (rx.empbuff.dump_mode == DUMP_MODE_EMP) {
if (rx.empbuff.pg_addr) {
dma_release_from_contiguous(dev,
@@ -2263,7 +2272,7 @@ static int hdmirx_probe(struct platform_device *pdev)
clk_rate/1000000);
}
#endif
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/*for audio clk measure*/
hdevp->meter_clk = clk_get(&pdev->dev, "cts_hdmirx_meter_clk");
if (IS_ERR(hdevp->meter_clk))

3
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -46,7 +46,7 @@
*
*
*/
#define RX_VER2 "ver.2019/03/19"
#define RX_VER2 "ver.2019/04/02"
/*print type*/
#define LOG_EN 0x01
@@ -86,6 +86,7 @@ enum chip_id_e {
CHIP_ID_TXLX,
CHIP_ID_TXHD,
CHIP_ID_TL1,
CHIP_ID_TM2,
};
enum phy_ver_e {

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c
View File

@@ -181,7 +181,7 @@ void eq_dwork_handler(struct work_struct *work)
cancel_delayed_work(&eq_dwork);
/* for tl1 no SW eq */
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
return;
for (i = 0; i < NTRYS; i++) {

80
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -116,7 +116,7 @@ unsigned int hdmirx_rd_dwc(unsigned int addr)
int data;
unsigned long dev_offset = 0x10;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(&reg_rw_lock, flags);
data = rd_reg(MAP_ADDR_MODULE_TOP,
addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr);
@@ -154,7 +154,7 @@ void hdmirx_wr_dwc(unsigned int addr, unsigned int data)
ulong flags;
unsigned int dev_offset = 0x10;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(&reg_rw_lock, flags);
wr_reg(MAP_ADDR_MODULE_TOP,
addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr, data);
@@ -288,7 +288,7 @@ unsigned int hdmirx_rd_top(unsigned int addr)
unsigned int dev_offset = 0;
unsigned int tempaddr = 0;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(&reg_rw_lock, flags);
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
@@ -337,7 +337,7 @@ void hdmirx_wr_top(unsigned int addr, unsigned int data)
unsigned long dev_offset = 0;
unsigned int tempaddr = 0;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(&reg_rw_lock, flags);
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
@@ -704,7 +704,7 @@ void hdmirx_phy_pddq(unsigned int enable)
uint32_t term_value =
hdmirx_rd_top(TOP_HPD_PWR5V) & 0x7;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL2, _BIT(1), enable);
/* set rxsense */
if (enable)
@@ -740,7 +740,7 @@ void hdmirx_top_sw_reset(void)
ulong flags;
unsigned long dev_offset = 0;
spin_lock_irqsave(&reg_rw_lock, flags);
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
wr_reg(MAP_ADDR_MODULE_TOP,
@@ -771,7 +771,7 @@ void rx_irq_en(bool enable)
unsigned int data32 = 0;
if (enable) {
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
data32 |= 1 << 31; /* DRC_CKS_CHG */
data32 |= 1 << 30; /* DRC_RCV */
data32 |= 0 << 29; /* AUD_TYPE_CHG */
@@ -1069,7 +1069,7 @@ bool is_clk_stable(void)
{
int clk = false;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* sqofclk */
clk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
} else {
@@ -1265,7 +1265,7 @@ static int TOP_init(void)
hdmirx_wr_top(TOP_VID_CNTL2, data32);
}
data32 = 0;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* n_cts_auto_mode: */
/* 0-every ACR packet */
/* 1-on N or CTS value change */
@@ -1273,12 +1273,12 @@ static int TOP_init(void)
}
/* delay cycles before n/cts update pulse */
data32 |= 7 << 0;
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
hdmirx_wr_top(TOP_TL1_ACR_CNTL2, data32);
else
hdmirx_wr_top(TOP_ACR_CNTL2, data32);
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
data32 = hdmirx_rd_dwc(DWC_HDCP_CTRL);
/* 0: Original behaviour */
/* 1: Balance path delay between non-HDCP and HDCP */
@@ -1515,7 +1515,7 @@ void rx_hdcp14_config(const struct hdmi_rx_hdcp *hdcp)
#if 0
void rx_set_term_enable(bool enable)
{
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* need to do : for tl1 */
} else
hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1,
@@ -1527,7 +1527,7 @@ void rx_set_term_value(unsigned char port, bool value)
{
unsigned int data32;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* need to do : for tl1 */
data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
if (port < E_PORT3) {
@@ -1625,7 +1625,7 @@ void rx_force_rxsense_cfg(uint8_t level)
unsigned int term_ovr_value;
unsigned int data32;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* enable terminal connect */
data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
if (level) {
@@ -1721,7 +1721,7 @@ void hdcp22_clk_en(bool en)
((0 << 25) |
(1 << 24) | /* [ 24] Enable gated clock */
(0 << 16)));
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
/* TL1:esm related clk bit9-11 */
hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 9), 0x7);
else
@@ -1739,7 +1739,7 @@ void hdcp22_clk_en(bool en)
void hdmirx_hdcp22_esm_rst(void)
{
/* For TL1,the sw_reset_hdcp22 bit is top reg 0x0,bit'12 */
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
hdmirx_wr_top(TOP_SW_RESET, 0x1000);
else
/* For txlx and previous chips,the sw_reset_hdcp22 is bit'8 */
@@ -1876,7 +1876,7 @@ void clk_init(void)
#endif
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD) ||
(rx.chip_id == CHIP_ID_TL1)) {
(rx.chip_id >= CHIP_ID_TL1)) {
/* [15] hdmirx_aud_pll4x_en override enable */
/* [14] hdmirx_aud_pll4x_en override value */
/* [6:5] clk_sel for cts_hdmirx_aud_pll_clk: */
@@ -1898,7 +1898,7 @@ void clk_init(void)
data32 |= 0 << 31; /* [31] disable clkgating */
data32 |= 1 << 17; /* [17] audfifo_rd_en */
data32 |= 1 << 16; /* [16] pktfifo_rd_en */
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
data32 |= 0 << 8; /* [8] tmds_ch2_clk_inv */
data32 |= 0 << 7; /* [7] tmds_ch1_clk_inv */
data32 |= 0 << 6; /* [6] tmds_ch0_clk_inv */
@@ -2004,7 +2004,7 @@ int hdmirx_audio_init(void)
data32 |= acr_mode << 0;
hdmirx_wr_top(TOP_ACR_CNTL_STAT, data32);
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
data32 = 0;
data32 |= 0 << 2;/*meas_mode*/
data32 |= 1 << 1;/*enable*/
@@ -2246,7 +2246,7 @@ void hdmirx_phy_init(void)
{
/* uint32_t data32; */
/* uint32_t cur_cable_clk; */
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
aml_phy_bw_switch();
else
snps_phyg3_init();
@@ -2283,7 +2283,7 @@ bool rx_clkrate_monitor(void)
if (clk_rate != rx.phy.clk_rate) {
changed = true;
if (rx.chip_id != CHIP_ID_TL1) {
if (rx.chip_id < CHIP_ID_TL1) {
for (i = 0; i < 3; i++) {
error = hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT,
CLK_RATE_BIT, clk_rate);
@@ -2409,7 +2409,7 @@ void hdmirx_hw_config(void)
hdmirx_20_init();
DWC_init();
hdmirx_irq_hdcp_enable(true);
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
aml_phy_switch_port();
hdmirx_phy_init();
hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
@@ -2441,7 +2441,7 @@ void hdmirx_hw_probe(void)
packet_init();
if (rx.chip_id != CHIP_ID_TXHD)
hdmirx_20_init();
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
aml_phy_switch_port();
hdmirx_phy_init();
hdmirx_wr_top(TOP_PORT_SEL, 0x10);
@@ -2527,7 +2527,7 @@ void rx_aud_pll_ctl(bool en)
int tmp = 0;
/*unsigned int od, od2;*/
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
if (en) {
/* AUD_CLK=N/CTS*TMDS_CLK */
/* bandgap enable */
@@ -2788,10 +2788,10 @@ int rx_get_clock(enum measure_clk_top_e clk_src)
if (clk_src == TOP_HDMI_TMDSCLK)
tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT);
else if (clk_src == TOP_HDMI_CABLECLK) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
tmp_data = hdmirx_rd_top(TOP_METER_CABLE_STAT);
} else if (clk_src == TOP_HDMI_AUDIOCLK) {
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/*get audio clk*/
tmp_data = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT0);
tmp_data2 = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT1);
@@ -2913,12 +2913,12 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
*/
if (clksrc == MEASURE_CLK_CABLE) {
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
clock = meson_clk_measure(30);
/*clock = rx_get_clock(TOP_HDMI_CABLECLK);*/
}
} else if (clksrc == MEASURE_CLK_TMDS) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(63);
else {
clock = meson_clk_measure(25);
@@ -2931,18 +2931,18 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
} else if (clksrc == MEASURE_CLK_PIXEL) {
clock = meson_clk_measure(29);
} else if (clksrc == MEASURE_CLK_AUD_PLL) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(74);/*audio vid out*/
else
clock = meson_clk_measure(24);
} else if (clksrc == MEASURE_CLK_AUD_DIV) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(67);/*apll_clk_audio*/
else
clock = meson_clk_measure(98);
} else if (clksrc == MEASURE_CLK_MPLL) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(29);/*apll_clk_out_div*/
else
clock = meson_clk_measure(27);
@@ -3072,7 +3072,7 @@ void dump_reg(void)
i = i + 4;
}
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
for (i = 0x25; i <= 0x84;) {
rx_pr("[0x%-3x]", i);
rx_pr("0x%-8x", hdmirx_rd_top(i));
@@ -3099,7 +3099,7 @@ void dump_reg(void)
i = i + 4;
}
} else if (rx.chip_id == CHIP_ID_TL1) {
} else if (rx.chip_id >= CHIP_ID_TL1) {
/* dump phy register */
rx_pr("\n***AML PHY registers***\n");
for (i = HHI_HDMIRX_APLL_CNTL0;
@@ -3251,7 +3251,7 @@ int rx_get_aud_pll_err_sts(void)
uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3;
uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3;
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/* need to do something ...*/
} else {
if (req_clk > PHY_REQUEST_CLK_MAX ||
@@ -3279,7 +3279,7 @@ uint32_t aml_cable_clk_band(uint32_t cableclk,
uint32_t bw;
uint32_t cab_clk = cableclk;
if (rx.chip_id != CHIP_ID_TL1)
if (rx.chip_id < CHIP_ID_TL1)
return phy_frq_band_2;
/* rx_pr("cable clk=%d, clkrate=%d\n", cableclk, clkrate); */
@@ -3683,7 +3683,7 @@ void rx_get_best_eq_setting(void)
static uint32_t time_cnt;
static uint32_t array_cnt;
if ((rx.chip_id != CHIP_ID_TL1) ||
if ((rx.chip_id < CHIP_ID_TL1) ||
(!find_best_eq))
return;
if ((find_best_eq >= 0x7777) ||
@@ -3934,7 +3934,7 @@ bool is_tmds_valid(void)
if (force_vic)
return true;
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
return (aml_phy_tmds_valid() == 1) ? true : false;
else
return (rx_get_pll_lock_sts() == 1) ? true : false;
@@ -3984,7 +3984,7 @@ void rx_phy_power_on(unsigned int onoff)
hdmirx_phy_pddq(0);
else
hdmirx_phy_pddq(1);
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
/*the enable of these regs are in phy init*/
if (onoff == 0) {
wr_reg_hhi_bits(HHI_HDMIRX_APLL_CNTL0, _BIT(28), onoff);
@@ -3999,7 +3999,7 @@ void rx_emp_to_ddr_init(void)
{
unsigned int data;
if (rx.chip_id != CHIP_ID_TL1)
if (rx.chip_id < CHIP_ID_TL1)
return;
if (rx.empbuff.pg_addr) {
@@ -4160,7 +4160,7 @@ void rx_tmds_to_ddr_init(void)
unsigned int data, data2;
unsigned int i = 0;
if (rx.chip_id != CHIP_ID_TL1)
if (rx.chip_id < CHIP_ID_TL1)
return;
if (rx.empbuff.pg_addr) {

8
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c
View File

@@ -185,7 +185,7 @@ void rx_pkt_debug(void)
data32 |= (rx_pkt_type_mapping(PKT_TYPE_ISRC1));
data32 |= (rx_pkt_type_mapping(PKT_TYPE_ISRC2));
data32 |= (rx_pkt_type_mapping(PKT_TYPE_GAMUT_META));
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
data32 |= (rx_pkt_type_mapping(PKT_TYPE_EMP));
hdmirx_wr_dwc(DWC_PDEC_CTRL, data32);
@@ -351,7 +351,7 @@ void rx_debug_pktinfo(char input[][20])
enable |= _BIT(30);/* DRC_RCV*/
else
enable |= _BIT(9);/* DRC_RCV*/
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
enable |= _BIT(9);/* EMP_RCV*/
enable |= _BIT(20);/* GMD_RCV */
enable |= _BIT(19);/* AIF_RCV */
@@ -394,7 +394,7 @@ void rx_debug_pktinfo(char input[][20])
else if (strncmp(input[2], "amp", 3) == 0)
sts = _BIT(14);
else if (strncmp(input[2], "emp", 3) == 0) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
sts = _BIT(9);
else
rx_pr("no emp function\n");
@@ -428,7 +428,7 @@ void rx_debug_pktinfo(char input[][20])
else if (strncmp(input[2], "amp", 3) == 0)
enable |= _BIT(14);
else if (strncmp(input[2], "emp", 3) == 0) {
if (rx.chip_id == CHIP_ID_TL1)
if (rx.chip_id >= CHIP_ID_TL1)
enable |= _BIT(9);
else
rx_pr("no emp function\n");

20
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -211,7 +211,7 @@ struct rx_s rx;
void hdmirx_init_params(void)
{
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
clk_unstable_max = 10;
esd_phy_rst_max = 20;
stable_check_lvl = 0x7df;
@@ -359,7 +359,7 @@ static int hdmi_rx_ctrl_irq_handler(void)
}
}
if (rx.chip_id != CHIP_ID_TL1) {
if (rx.chip_id < CHIP_ID_TL1) {
rx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
if (rx_top_intr_stat & _BIT(31))
irq_need_clr = 1;
@@ -419,7 +419,7 @@ static int hdmi_rx_ctrl_irq_handler(void)
rx_pr("[irq] FIFO MIN\n");
}
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
if (rx_get_bits(intr_pedc,
_BIT(9)) != 0) {
if (log_level & 0x400)
@@ -522,7 +522,7 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
hdmirx_wr_top(TOP_INTR_STAT_CLR, hdmirx_top_intr_stat);
/* modify interrupt flow for isr loading */
/* top interrupt handler */
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
if (hdmirx_top_intr_stat & (1 << 29))
if (log_level & 0x100)
rx_pr("[isr] sqofclk_fall\n");
@@ -559,7 +559,7 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
rx_pr("[isr] enc fall\n");
/* must clear ip interrupt quickly */
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
hdmirx_top_intr_stat &= 0x1;
} else {
hdmirx_top_intr_stat &= (~(1 << 30));
@@ -576,7 +576,7 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
}
}
if (rx.chip_id != CHIP_ID_TL1) {
if (rx.chip_id < CHIP_ID_TL1) {
if (error == 1)
goto reisr;
} else {
@@ -1994,7 +1994,7 @@ void rx_monitor_error_counter(void)
ulong timestap;
uint32_t ch0, ch1, ch2;
if (rx.chip_id != CHIP_ID_TL1)
if (rx.chip_id < CHIP_ID_TL1)
return;
timestap = get_seconds();
@@ -2033,7 +2033,7 @@ void rx_err_monitor(void)
break;
case ERR_PHY_UNLOCK:
if (err_dbg_cnt == 0) {
if (rx.chip_id != CHIP_ID_TL1)
if (rx.chip_id < CHIP_ID_TL1)
rx_pr("EQ = %d-%d-%d\n",
eq_ch0.bestsetting,
eq_ch1.bestsetting,
@@ -2519,7 +2519,7 @@ static void dump_phy_status(void)
uint32_t val0, val1, val2;
rx_pr("[PHY info]\n");
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
rx_get_error_cnt(&val0, &val1, &val2);
rx_pr("err cnt- ch0: %d,ch1:%d ch2:%d\n", val0, val1, val2);
rx_pr("PLL_LCK_STS(tmds valid) = 0x%x\n",
@@ -2606,7 +2606,7 @@ static void dump_audio_status(void)
rx_pr(" CA=%u\n", a.auds_ch_alloc);
rx_pr("CTS=%d, N=%d,", a.cts, a.n);
rx_pr("acr clk=%d\n", a.arc);
if (rx.chip_id == CHIP_ID_TL1) {
if (rx.chip_id >= CHIP_ID_TL1) {
rx_get_audio_N_CTS(&val0, &val1);
rx_pr("top CTS:%d, N:%d\n", val1, val0);
}