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media: rockchip: cif: aligned bytesperline with 256 for raw compact

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to optimize reading and writing of ddr, aliged with 256,
sync with virtual width

Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I5cb7e3a08e8805371eeac30cd992f97a0c759076
This commit is contained in:
Allon Huang
2020-09-10 11:34:26 +08:00
committed by Cai YiWei
parent dcdfbf8484
commit 811474ebbf
1 changed files with 6 additions and 4 deletions
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10
drivers/media/platform/rockchip/cif/capture.c
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@@ -1329,10 +1329,11 @@ static int rkcif_csi_channel_init(struct rkcif_stream *stream,
/*
* for mipi or lvds, when enable compact, the virtual width of raw10/raw12
* needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
* needs aligned with :ALIGN(bits_per_pixel * width * 2, 8)
* needs aligned with :ALIGN(bits_per_pixel * width * 2, 8), to optimize reading and
* writing of ddr, aliged with 256
*/
if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact) {
channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 8);
channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
} else {
if (fmt->fmt_type == CIF_FMT_TYPE_RAW)
channel->virtual_width = ALIGN(channel->width * 2, 8);
@@ -2377,12 +2378,13 @@ static void rkcif_set_fmt(struct rkcif_stream *stream,
}
/* compact mode need bytesperline 4bytes align,
* align 8 to bring into correspondence with virtual width
* align 8 to bring into correspondence with virtual width.
* to optimize reading and writing of ddr, aliged with 256.
*/
if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
(dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 ||
dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
bpl = ALIGN(width * fmt->raw_bpp / 8, 8);
bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
} else {
bpp = rkcif_align_bits_per_pixel(fmt, i);
bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;