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hdmirx: txl: add support for txl

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PD#168480: hdmirx: txl: add support for txl

Change-Id: Ia1216721f2732052c5c3a5384a3dc01ffacb9392
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
This commit is contained in:
Hang Cheng
2018-06-26 15:03:55 +08:00
committed by Yixun Lan
parent 54ba3b89c3
commit 811568bdef
5 changed files with 41 additions and 24 deletions
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7
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
View File

@@ -166,7 +166,7 @@ static const struct of_device_id hdmirx_dt_match[] = {
.data = &rx_txlx_data
},
{
.compatible = "amlogic, hdmirx_txl",
.compatible = "amlogic, hdmirx-txl",
.data = &rx_txl_data
},
{
@@ -923,7 +923,7 @@ static long hdmirx_ioctl(struct file *file, unsigned int cmd,
#if 0
else {
if (hdmi_cec_en) {
if (is_meson_gxtvbb_cpu())
if (rx.chip_id == CHIP_ID_GXTVBB)
rx_force_hpd_cfg(0);
else
rx_force_hpd_cfg(1);
@@ -1720,7 +1720,8 @@ static int hdmirx_probe(struct platform_device *pdev)
clk_rate = clk_get_rate(hdevp->skp_clk);
}
}
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) {
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD)) {
tmds_clk_fs = clk_get(&pdev->dev, "hdmirx_aud_pll2fs");
if (IS_ERR(tmds_clk_fs))
rx_pr("get tmds_clk_fs err\n");

4
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -41,7 +41,7 @@
*
*
*/
#define RX_VER1 "ver.2018/06/07"
#define RX_VER1 "ver.2018/06/26"
/*
*
*
@@ -74,7 +74,7 @@ enum chip_id_e {
CHIP_ID_GXTVBB,
CHIP_ID_TXL,
CHIP_ID_TXLX,
CHIP_ID_TXHD = CHIP_ID_TXLX,
CHIP_ID_TXHD,
};
struct meson_hdmirx_data {

21
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -571,7 +571,7 @@ void rx_irq_en(bool enable)
unsigned int data32 = 0;
if (enable) {
if (is_meson_txlx_cpu()) {
if (rx.chip_id == CHIP_ID_TXLX) {
data32 |= 1 << 31; /* DRC_CKS_CHG */
data32 |= 1 << 30; /* DRC_RCV */
data32 |= 0 << 29; /* AUD_TYPE_CHG */
@@ -598,7 +598,7 @@ void rx_irq_en(bool enable)
data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */
data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */
data32 |= pdec_ists_en;
} else if (is_meson_txhd_cpu()) {
} else if (rx.chip_id == CHIP_ID_TXHD) {
/* data32 |= 1 << 31; DRC_CKS_CHG */
/* data32 |= 1 << 30; DRC_RCV */
data32 |= 0 << 29; /* AUD_TYPE_CHG */
@@ -777,7 +777,7 @@ unsigned int rx_get_hpd_sts(void)
*/
unsigned int rx_get_scdc_clkrate_sts(void)
{
if (is_meson_txhd_cpu())
if (rx.chip_id == CHIP_ID_TXHD)
return 0;
else
return (hdmirx_rd_dwc(DWC_SCDC_REGS0) >> 17) & 1;
@@ -859,7 +859,7 @@ int hdmirx_control_clk_range(unsigned long min, unsigned long max)
*/
void set_scdc_cfg(int hpdlow, int pwrprovided)
{
if (is_meson_txhd_cpu())
if (rx.chip_id == CHIP_ID_TXHD)
return;
hdmirx_wr_dwc(DWC_SCDC_CONFIG,
@@ -969,7 +969,7 @@ static int TOP_init(void)
data32 |= 0 << 0;
hdmirx_wr_top(TOP_VID_CNTL, data32);
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
data32 = 0;
data32 |= 0 << 20;
data32 |= 0 << 8;
@@ -1128,7 +1128,7 @@ void rx_hdcp14_config(const struct hdmi_rx_hdcp *hdcp)
}
hdmirx_wr_dwc(DWC_HDCP_BKSV1, hdcp->bksv[0]);
hdmirx_wr_dwc(DWC_HDCP_BKSV0, hdcp->bksv[1]);
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL,
REPEATER, hdcp->repeat ? 1 : 0);
/* nothing attached downstream */
@@ -1355,7 +1355,8 @@ void clk_init(void)
data32 |= 2 << 0;
wr_reg_hhi(HHI_HDMIRX_AUD_CLK_CNTL, data32);
#endif
if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) {
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD)) {
/* [15] hdmirx_aud_pll4x_en override enable */
/* [14] hdmirx_aud_pll4x_en override value */
/* [6:5] clk_sel for cts_hdmirx_aud_pll_clk: */
@@ -1667,7 +1668,7 @@ bool rx_clkrate_monitor(void)
int i;
int error = 0;
if (is_meson_txhd_cpu())
if (rx.chip_id == CHIP_ID_TXHD)
return false;
if (force_clk_rate & 0x10)
@@ -1738,7 +1739,7 @@ void hdmirx_hw_config(void)
rx_hdcp_init();
hdmirx_audio_init();
packet_init();
if (!is_meson_txhd_cpu())
if (rx.chip_id != CHIP_ID_TXHD)
hdmirx_20_init();
DWC_init();
hdmirx_irq_hdcp_enable(true);
@@ -1766,7 +1767,7 @@ void hdmirx_hw_probe(void)
hdcp22_clk_en(1);
hdmirx_audio_init();
packet_init();
if (!is_meson_txhd_cpu())
if (rx.chip_id != CHIP_ID_TXHD)
hdmirx_20_init();
hdmirx_phy_init();
hdmirx_wr_top(TOP_PORT_SEL, 0x10);

19
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c
View File

@@ -168,7 +168,7 @@ void rx_pkt_debug(void)
data32 |= (rx_pkt_type_mapping(PKT_TYPE_INFOFRAME_AUD));
data32 |= (rx_pkt_type_mapping(PKT_TYPE_INFOFRAME_VSI));
data32 |= (rx_pkt_type_mapping(PKT_TYPE_INFOFRAME_MPEGSRC));
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
data32 |= (rx_pkt_type_mapping(PKT_TYPE_INFOFRAME_NVBI));
data32 |= (rx_pkt_type_mapping(PKT_TYPE_INFOFRAME_DRM));
data32 |= (rx_pkt_type_mapping(PKT_TYPE_AUD_META));
@@ -337,7 +337,8 @@ void rx_debug_pktinfo(char input[][20])
rx_pr("pdec_ists_en=0x%x\n", pdec_ists_en);
rx_irq_en(1);
} else if (strncmp(input[1], "debugext", 8) == 0) {
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD))
enable |= _BIT(30);/* DRC_RCV*/
else
enable |= _BIT(9);/* DRC_RCV*/
@@ -362,7 +363,8 @@ void rx_debug_pktinfo(char input[][20])
if (strncmp(input[2], "fifo", 4) == 0)
sts = (PD_FIFO_START_PASS|PD_FIFO_OVERFL);
else if (strncmp(input[2], "drm", 3) == 0) {
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD))
sts = _BIT(30);
else
sts = _BIT(9);
@@ -390,7 +392,8 @@ void rx_debug_pktinfo(char input[][20])
if (strncmp(input[2], "fifo", 4) == 0)
enable |= (PD_FIFO_START_PASS|PD_FIFO_OVERFL);
else if (strncmp(input[2], "drm", 3) == 0) {
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD))
enable |= _BIT(30);
else
enable |= _BIT(9);
@@ -1084,7 +1087,7 @@ void rx_pkt_get_vsi_ex(void *pktinfo)
pkt->ver_st.version = 0;
pkt->ver_st.chgbit = 0;
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
pkt->sbpkt.payload.data[0] =
hdmirx_rd_dwc(DWC_PDEC_VSI_PLAYLOAD0);
pkt->sbpkt.payload.data[1] =
@@ -1112,7 +1115,7 @@ void rx_pkt_get_amp_ex(void *pktinfo)
}
/*memset(pkt, 0, sizeof(struct pd_infoframe_s));*/
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
HB = hdmirx_rd_dwc(DWC_PDEC_AMP_HB);
pkt->HB = (HB << 8) | PKT_TYPE_AUD_META;
pkt->PB0 = hdmirx_rd_dwc(DWC_PDEC_AMP_PB0);
@@ -1192,7 +1195,7 @@ void rx_pkt_get_drm_ex(void *pktinfo)
}
drmpkt->pkttype = PKT_TYPE_INFOFRAME_DRM;
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
drmpkt->length = (hdmirx_rd_dwc(DWC_PDEC_DRM_HB) >> 8);
drmpkt->version = hdmirx_rd_dwc(DWC_PDEC_DRM_HB);
@@ -1223,7 +1226,7 @@ void rx_pkt_get_ntscvbi_ex(void *pktinfo)
return;
}
if (!is_meson_txhd_cpu()) {
if (rx.chip_id != CHIP_ID_TXHD) {
/*byte 0 , 1*/
pkt->HB = hdmirx_rd_dwc(DWC_PDEC_NTSCVBI_HB);
pkt->PB0 = hdmirx_rd_dwc(DWC_PDEC_NTSCVBI_PB0);

14
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -384,7 +384,7 @@ static int hdmi_rx_ctrl_irq_handler(void)
if (log_level & 0x200)
rx_pr("[irq] FIFO MIN\n");
}
if (!is_meson_txlx_cpu()) {
if (rx.chip_id != CHIP_ID_TXLX) {
if (rx_get_bits(intr_pedc,
DRM_RCV_EN) != 0) {
if (log_level & 0x400)
@@ -2921,6 +2921,18 @@ int hdmirx_debug(const char *buf, int size)
rx_pr("Hdmirx version1: %s\n", RX_VER1);
rx_pr("Hdmirx version2: %s\n", RX_VER2);
rx_pr("------------------\n");
} else if (strncmp(input[0], "port0", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI0);
rx.open_fg = 1;
} else if (strncmp(input[0], "port1", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI1);
rx.open_fg = 1;
} else if (strncmp(input[0], "port2", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI2);
rx.open_fg = 1;
} else if (strncmp(input[0], "port3", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI3);
rx.open_fg = 1;
}
return 0;
}