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dtsi: arm64: rockchip: add rk3366 dtsi file
Change-Id: I5a4d3b904f458e2a0df1a0055c97bf5b10b2905f Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu
committed by
Gerrit Code Review
Gerrit Code Review
parent
4b4ca6f00b
commit
82cfabe7d7
719
arch/arm64/boot/dts/rockchip/rk3366.dtsi
Normal file
719
arch/arm64/boot/dts/rockchip/rk3366.dtsi
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@@ -0,0 +1,719 @@
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/*
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* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rk3366-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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compatible = "rockchip,rk3366";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &uart0;
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serial2 = &uart2;
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serial3 = &uart3;
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spi0 = &spi0;
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spi1 = &spi1;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <
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GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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};
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gic: interrupt-controller@ffb71000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x0 0xffb71000 0x0 0x1000>,
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<0x0 0xffb72000 0x0 0x1000>,
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<0x0 0xffb74000 0x0 0x2000>,
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<0x0 0xffb76000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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saradc: saradc@ff100000 {
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compatible = "rockchip,saradc";
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reg = <0x0 0xff100000 0x0 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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status = "disabled";
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};
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spi0: spi@ff110000 {
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compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff110000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@ff120000 {
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compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@ff650000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff728000 0x0 0x1000>;
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clocks = <&cru PCLK_I2C0>;
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clock-names = "i2c";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@ff140000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff140000 0x0 0x1000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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i2c3: i2c@ff150000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff150000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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i2c4: i2c@ff160000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff160000 0x0 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C4>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_xfer>;
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff170000 0x0 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C5>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_xfer>;
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status = "disabled";
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff180000 0x0 0x100>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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uart3: serial@ff1b0000 {
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compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff1b0000 0x0 0x100>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
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status = "disabled";
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};
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i2c1: i2c@ff660000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff660000 0x0 0x1000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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pwm0: pwm@ff680000 {
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compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
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reg = <0x0 0xff680000 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm1: pwm@ff680010 {
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compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
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reg = <0x0 0xff680010 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm2: pwm@ff680020 {
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compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
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reg = <0x0 0xff680020 0x0 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm3: pwm@ff680030 {
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compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
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reg = <0x0 0xff680030 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_t2_pin>;
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clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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uart2: serial@ff690000 {
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compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff690000 0x0 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_t1_xfer>;
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status = "disabled";
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};
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pmugrf: syscon@ff738000 {
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compatible = "rockchip,rk3366-pmugrf", "syscon";
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reg = <0x0 0xff738000 0x0 0x1000>;
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};
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cru: clock-controller@ff760000 {
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compatible = "rockchip,rk3366-cru";
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reg = <0x0 0xff760000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3366-grf", "syscon";
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reg = <0x0 0xff770000 0x0 0x1000>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3366-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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gpio0: gpio0@ff750000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff750000 0x0 0x100>;
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clocks = <&cru PCLK_GPIO0>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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};
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gpio1: gpio1@ff780000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff758000 0x0 0x100>;
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clocks = <&cru PCLK_GPIO1>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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};
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gpio2: gpio2@ff790000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff790000 0x0 0x100>;
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clocks = <&cru PCLK_GPIO2>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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};
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gpio3: gpio3@ff7a0000 {
|
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compatible = "rockchip,gpio-bank";
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reg = <0x0 0xff7a0000 0x0 0x100>;
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clocks = <&cru PCLK_GPIO3>;
|
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
|
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};
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||||
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gpio4: gpio4@ff7b0000 {
|
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compatible = "rockchip,gpio-bank";
|
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reg = <0x0 0xff7b0000 0x0 0x100>;
|
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clocks = <&cru PCLK_GPIO4>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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||||
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gpio-controller;
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#gpio-cells = <0x2>;
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||||
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interrupt-controller;
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#interrupt-cells = <0x2>;
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||||
};
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||||
|
||||
gpio5: gpio5@ff7c0000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff7c0000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_GPIO5>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins =
|
||||
<3 4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins =
|
||||
<2 26 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_pwr: emmc-pwr {
|
||||
rockchip,pins =
|
||||
<2 27 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus1: emmc-bus1 {
|
||||
rockchip,pins =
|
||||
<2 18 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus4: emmc-bus4 {
|
||||
rockchip,pins =
|
||||
<2 18 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 19 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 20 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 21 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins =
|
||||
<2 18 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 19 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 20 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 21 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 22 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 23 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 24 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<2 25 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins =
|
||||
<0 3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins =
|
||||
<4 19 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 20 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
i2c2_xfer: i2c2-xfer {
|
||||
rockchip,pins =
|
||||
<5 15 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<5 16 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
i2c3_xfer: i2c3-xfer {
|
||||
rockchip,pins =
|
||||
<2 16 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<2 17 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4 {
|
||||
i2c4_xfer: i2c4-xfer {
|
||||
rockchip,pins =
|
||||
<5 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<5 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5 {
|
||||
i2c5_xfer: i2c5-xfer {
|
||||
rockchip,pins =
|
||||
<5 13 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<5 14 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s {
|
||||
i2s_8ch_bus: i2s-8ch-bus {
|
||||
rockchip,pins =
|
||||
<4 16 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 17 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 18 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 19 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 20 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 21 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 22 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 23 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<4 24 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
spi0_clk: spi0-clk {
|
||||
rockchip,pins =
|
||||
<2 29 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_cs0: spi0-cs0 {
|
||||
rockchip,pins =
|
||||
<2 24 RK_FUNC_3 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_cs1: spi0-cs1 {
|
||||
rockchip,pins =
|
||||
<2 25 RK_FUNC_3 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_tx: spi0-tx {
|
||||
rockchip,pins =
|
||||
<2 23 RK_FUNC_3 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_rx: spi0-rx {
|
||||
rockchip,pins =
|
||||
<2 22 RK_FUNC_3 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
spi1_clk: spi1-clk {
|
||||
rockchip,pins =
|
||||
<2 4 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_cs0: spi1-cs0 {
|
||||
rockchip,pins =
|
||||
<2 5 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_rx: spi1-rx {
|
||||
rockchip,pins =
|
||||
<2 6 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_tx: spi1-tx {
|
||||
rockchip,pins =
|
||||
<2 7 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins =
|
||||
<3 8 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<3 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins =
|
||||
<3 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins =
|
||||
<3 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_t0 {
|
||||
uart2_t0_xfer: uart2_t0-xfer {
|
||||
rockchip,pins =
|
||||
<0 22 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<0 21 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart2_t1 {
|
||||
uart2_t1_xfer: uart2_t1-xfer {
|
||||
rockchip,pins =
|
||||
<5 0 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<5 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart2_t2 {
|
||||
uart2_t2_xfer: uart2_t2-xfer {
|
||||
rockchip,pins =
|
||||
<5 14 RK_FUNC_3 &pcfg_pull_up>,
|
||||
<5 13 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins =
|
||||
<5 15 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<5 16 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins =
|
||||
<5 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins =
|
||||
<5 18 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_pin: pwm0-pin {
|
||||
rockchip,pins =
|
||||
<0 8 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
rockchip,pins =
|
||||
<1 6 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2_t0 {
|
||||
pwm2_t0_pin: pwm2_t0-pin {
|
||||
rockchip,pins =
|
||||
<2 15 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2_t1 {
|
||||
pwm2_t1_pin: pwm2_t1-pin {
|
||||
rockchip,pins =
|
||||
<5 17 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_t0 {
|
||||
pwm3_t0_pin: pwm3_t0-pin {
|
||||
rockchip,pins =
|
||||
<1 0 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_t1 {
|
||||
pwm3_t1_pin: pwm3_t1-pin {
|
||||
rockchip,pins =
|
||||
<0 21 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_t2 {
|
||||
pwm3_t2_pin: pwm3_t2-pin {
|
||||
rockchip,pins =
|
||||
<5 18 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user