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drm/rockchip: vop2: update the calculation of dclk_out division factor for RK3588 HDMI DSC mode

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For RK3588, dclk_out is designed for DP, MIPI in both DSC and non-DSC
mode and HDMI in DSC mode.

In addditon, the dclk_out division factor should be the same as the
dclk_core division factor in HDMI DSC mode.

Change-Id: I08107a340036ff9984f52dd34044d8c634df14c1
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2025-03-28 16:18:38 +08:00
committed by Tao Huang
parent 122ffa74f5
commit 8332740f6c
1 changed files with 13 additions and 2 deletions
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15
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -9207,6 +9207,11 @@ static int vop2_calc_if_clk(struct drm_crtc *crtc, const struct vop2_connector_i
if (vcstate->dsc_enable) {
hdmi_edp_pixclk = vcstate->dsc_cds_clk_rate << 1;
hdmi_edp_dclk = vcstate->dsc_cds_clk_rate;
/*
* For HDMI DSC mode, the dclk_out_rate should be the same
* as dclk_core_rate.
*/
dclk_out_rate = dclk_core_rate;
} else {
hdmi_edp_pixclk = (dclk_core_rate << 1) / K;
hdmi_edp_dclk = dclk_core_rate / K;
@@ -9284,13 +9289,19 @@ static int vop2_calc_if_clk(struct drm_crtc *crtc, const struct vop2_connector_i
}
}
/*
* For RK3588, dclk_out is designed for DP, MIPI(both DSC and non-DSC mode)
* and HDMI in DSC mode.
*/
if (dclk_core_rate > if_pixclk->rate) {
clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
if (output_if_is_mipi(conn_id))
if (output_if_is_mipi(conn_id) ||
(output_if_is_hdmi(conn_id) && vcstate->dsc_enable))
clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
ret = vop2_cru_set_rate(if_pixclk, if_dclk);
} else {
if (output_if_is_mipi(conn_id))
if (output_if_is_mipi(conn_id) ||
(output_if_is_hdmi(conn_id) && vcstate->dsc_enable))
clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
ret = vop2_cru_set_rate(if_pixclk, if_dclk);
clk_set_rate(dclk_core->hw.clk, dclk_core_rate);