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drm/rockchip: vop2: add support rk3576
RK3576 VOP have 2 Cluster win and 4 Esmart win, this win be used by 3 video ports as following roles: * VP0 can use Cluster0/1 and Esmart0/2 * VP1 can use Cluster0/1 and Esmart1/3 * VP2 can use Esmart0/1/2/3 In additions, RK3576 VOP can support DCI/ACM/CSC/HDR/SHARP/GAMMA/3D LUT/POST SCALE/BCSH etc. post process. Signed-off-by: Sandy Huang <hjc@rock-chips.com> Change-Id: I89f656e847f758f9d3d57ee0c137b29196de6737
This commit is contained in:
Sandy Huang
@@ -53,6 +53,7 @@ struct iommu_domain;
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#define VOP_OUTPUT_IF_DP1 BIT(10)
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#define VOP_OUTPUT_IF_HDMI0 BIT(11)
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#define VOP_OUTPUT_IF_HDMI1 BIT(12)
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#define VOP_OUTPUT_IF_DP2 BIT(13)
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#ifndef DRM_FORMAT_NV20
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#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
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@@ -29,6 +29,7 @@
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#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
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#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
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#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
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#define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765)
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#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
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/* register one connector */
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@@ -56,6 +57,8 @@
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#define VOP_FEATURE_VIVID_HDR BIT(7)
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#define VOP_FEATURE_POST_ACM BIT(8)
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#define VOP_FEATURE_POST_CSC BIT(9)
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#define VOP_FEATURE_POST_FRC_V2 BIT(10)
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#define VOP_FEATURE_POST_SHARP BIT(11)
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#define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
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@@ -78,6 +81,7 @@
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#define WIN_FEATURE_MIRROR BIT(6)
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#define WIN_FEATURE_MULTI_AREA BIT(7)
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#define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
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#define WIN_FEATURE_DCI BIT(9)
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#define VOP2_SOC_VARIANT 4
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@@ -124,6 +128,8 @@ enum vop3_esmart_lb_mode {
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VOP3_ESMART_4K_4K_MODE,
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VOP3_ESMART_4K_2K_2K_MODE,
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VOP3_ESMART_2K_2K_2K_2K_MODE,
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VOP3_ESMART_4K_4K_4K_MODE,
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VOP3_ESMART_4K_4K_2K_2K_MODE,
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};
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/*
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@@ -144,6 +150,7 @@ enum vop3_esmart_lb_mode {
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#define VOP2_PD_DSC_8K BIT(5)
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#define VOP2_PD_DSC_4K BIT(6)
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#define VOP2_PD_ESMART BIT(7)
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#define VOP2_PD_CLUSTER BIT(8)
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/*
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* vop2 submem power gate,
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@@ -238,6 +245,10 @@ struct vop_afbc {
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struct vop_reg transform_offset;
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struct vop_reg hdr_ptr;
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struct vop_reg half_block_en;
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struct vop_reg pld_offset_en;
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struct vop_reg pld_ptr_offset;
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struct vop_reg pld_range_en;
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struct vop_reg pld_ptr_range;
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struct vop_reg xmirror;
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struct vop_reg ymirror;
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struct vop_reg rotate_270;
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@@ -725,6 +736,8 @@ struct vop2_scl_regs {
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struct vop_reg cbcr_hscl_filter_mode;
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struct vop_reg cbcr_hor_scl_mode;
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struct vop_reg cbcr_vscl_filter_mode;
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struct vop_reg zme_dering_en;
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struct vop_reg zme_dering_para;
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struct vop_reg vsd_cbcr_gt2;
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struct vop_reg vsd_cbcr_gt4;
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struct vop_reg vsd_yrgb_gt2;
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@@ -745,6 +758,7 @@ struct vop2_win_regs {
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struct vop_reg gate;
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struct vop_reg enable;
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struct vop_reg format;
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struct vop_reg format_argb1555;
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struct vop_reg tile_mode;
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struct vop_reg csc_mode;
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struct vop_reg csc_13bit_en;
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@@ -762,6 +776,7 @@ struct vop2_win_regs {
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struct vop_reg yuv_clip;
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struct vop_reg lb_mode;
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struct vop_reg y2r_en;
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struct vop_reg csc_y2r_path_sel;
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struct vop_reg r2y_en;
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struct vop_reg channel;
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struct vop_reg dst_alpha_ctl;
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@@ -811,14 +826,15 @@ struct vop2_video_port_regs {
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struct vop_reg dither_up_en;
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struct vop_reg bg_dly;
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struct vop_reg core_dclk_div;
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struct vop_reg p2i_en;
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struct vop_reg dual_channel_en;
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struct vop_reg dual_channel_swap;
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struct vop_reg dsp_lut_en;
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struct vop_reg dclk_div2;
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struct vop_reg dclk_div2_phase_lock;
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struct vop_reg core_dclk_div; /* dclk core */
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struct vop_reg dclk_div2; /* dclk out */
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struct vop_reg dclk_div2_phase_lock; /* used to adjust phase when yuv420 output */
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struct vop_reg hdr10_en;
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struct vop_reg hdr_lut_update_en;
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@@ -937,6 +953,7 @@ struct vop2_power_domain_regs {
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struct vop_reg pd;
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struct vop_reg status;
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struct vop_reg bisr_en_status;
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struct vop_reg otp_bisr_en_status;
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struct vop_reg pmu_status;
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};
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@@ -995,11 +1012,15 @@ struct vop2_wb_regs {
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struct vop_reg scale_y_en;
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struct vop_reg axi_yrgb_id;
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struct vop_reg axi_uv_id;
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struct vop_reg vir_stride;
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struct vop_reg vir_stride_en;
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struct vop_reg act_width;
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struct vop_reg one_frame_mode;
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};
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struct vop2_power_domain_data {
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uint8_t id;
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uint8_t parent_id;
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uint16_t id;
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uint16_t parent_id;
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/*
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* @module_id_mask: module id of which module this power domain is belongs to.
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* PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3
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@@ -1029,7 +1050,7 @@ struct vop2_win_data {
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const char *name;
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uint8_t phys_id;
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uint8_t splice_win_id;
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uint8_t pd_id;
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uint16_t pd_id;
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uint8_t axi_id;
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uint8_t axi_yrgb_id;
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uint8_t axi_uv_id;
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@@ -1074,7 +1095,7 @@ struct dsc_error_info {
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struct vop2_dsc_data {
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uint8_t id;
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uint8_t pd_id;
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uint16_t pd_id;
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uint8_t max_slice_num;
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uint8_t max_linebuf_depth; /* used to generate the bitstream */
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uint8_t min_bits_per_pixel; /* bit num after encoder compress */
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@@ -1103,6 +1124,7 @@ struct vop3_ovl_mix_regs {
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struct vop3_ovl_regs {
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const struct vop3_ovl_mix_regs *layer_mix_regs;
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const struct vop3_ovl_mix_regs *hdr_mix_regs;
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const struct vop3_ovl_mix_regs *extra_mix_regs;
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};
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struct vop2_video_port_data {
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@@ -1121,6 +1143,7 @@ struct vop2_video_port_data {
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const u8 layer_mix_dly;
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const u8 hdr_mix_dly;
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const u8 win_dly;
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const u8 pixel_rate;
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const struct vop_intr *intr;
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const struct vop_hdr_table *hdr_table;
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const struct vop2_video_port_regs *regs;
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@@ -1208,16 +1231,21 @@ struct vop2_ctrl {
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struct vop_reg version;
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struct vop_reg standby;
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struct vop_reg dma_stop;
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struct vop_reg rkmmu_v2_en;
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struct vop_reg rkmmu_v2_sel_axi;
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struct vop_reg dsp_vs_t_sel;
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struct vop_reg lut_dma_en;
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struct vop_reg axi_outstanding_max_num;
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struct vop_reg axi_max_outstanding_en;
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struct vop_reg hdmi_dclk_out_en;
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struct vop_reg hdmi0_r2y_en;
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struct vop_reg hdmi0_r2y_mode;
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struct vop_reg rgb_en;
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struct vop_reg hdmi0_en;
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struct vop_reg hdmi1_en;
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struct vop_reg dp0_en;
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struct vop_reg dp1_en;
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struct vop_reg dp2_en;
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struct vop_reg edp0_en;
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struct vop_reg edp1_en;
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struct vop_reg mipi0_en;
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@@ -1244,10 +1272,13 @@ struct vop2_ctrl {
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struct vop_reg dp0_pin_pol;
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struct vop_reg dp1_dclk_pol;
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struct vop_reg dp1_pin_pol;
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struct vop_reg dp2_dclk_pol;
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struct vop_reg dp2_pin_pol;
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/* This will be reference by win_phy_id */
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struct vop_reg win_vp_id[16];
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struct vop_reg win_dly[16];
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struct vop_reg win_alpha_map[16];
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/* connector mux */
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struct vop_reg rgb_mux;
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@@ -1255,6 +1286,7 @@ struct vop2_ctrl {
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struct vop_reg hdmi1_mux;
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struct vop_reg dp0_mux;
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struct vop_reg dp1_mux;
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struct vop_reg dp2_mux;
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struct vop_reg edp0_mux;
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struct vop_reg edp1_mux;
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struct vop_reg mipi0_mux;
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@@ -1270,9 +1302,10 @@ struct vop2_ctrl {
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struct vop_reg edp_dual_en;
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struct vop_reg hdmi_dual_en;
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struct vop_reg mipi_dual_en;
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struct vop_reg rgb_dual_en;
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struct vop_reg hdmi0_dclk_div;
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struct vop_reg hdmi0_pixclk_div;
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struct vop_reg hdmi0_pixclk_div;/* crtc last pipeline clk to connector */
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struct vop_reg edp0_dclk_div;
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struct vop_reg edp0_pixclk_div;
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@@ -1286,6 +1319,18 @@ struct vop2_ctrl {
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struct vop_reg mipi0_ds_mode;
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struct vop_reg mipi1_ds_mode;
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struct vop_reg hdmi0_dclk_sel;/* sel from dclk_core or dclk_out */
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struct vop_reg edp0_dclk_sel;
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struct vop_reg mipi0_dclk_sel;
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struct vop_reg rgb_dclk_sel;
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struct vop_reg dp0_dclk_sel;
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struct vop_reg dp1_dclk_sel;
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struct vop_reg dp2_dclk_sel;
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struct vop_reg dp0_pixclk_div;/* crtc last pipeline clk to connector */
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struct vop_reg dp1_pixclk_div;
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struct vop_reg dp2_pixclk_div;
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struct vop_reg src_color_ctrl;
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struct vop_reg dst_color_ctrl;
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struct vop_reg src_alpha_ctrl;
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@@ -1296,8 +1341,31 @@ struct vop2_ctrl {
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struct vop_reg gamma_port_sel;
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struct vop_reg pd_off_imd;
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struct vop_reg mipi0_regdone_imd_en;
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struct vop_reg mipi0_data1_sel;
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struct vop_reg mipi0_dclk_out_en;
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struct vop_reg hdmi0_regdone_imd_en;
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struct vop_reg hdmi0_data1_sel;
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struct vop_reg hdmi0_dclk_out_en;
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struct vop_reg edp0_regdone_imd_en;
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struct vop_reg edp0_data1_sel;
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struct vop_reg edp0_dclk_out_en;
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struct vop_reg dp0_regdone_imd_en;
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struct vop_reg dp0_data1_sel;
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struct vop_reg dp0_dclk_out_en;
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struct vop_reg dp1_regdone_imd_en;
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struct vop_reg dp1_data1_sel;
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struct vop_reg dp1_dclk_out_en;
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struct vop_reg dp2_regdone_imd_en;
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struct vop_reg dp2_data1_sel;
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struct vop_reg dp2_dclk_out_en;
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struct vop_reg rgb_regdone_imd_en;
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struct vop_reg rgb_data1_sel;
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struct vop_reg rgb_dclk_out_en;
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struct vop_reg otp_en;
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struct vop_reg esmart_lb_mode;
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struct vop_reg vp_intr_merge_en;
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struct vop_reg reg_done_frm;
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struct vop_reg cfg_done;
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};
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@@ -1307,6 +1375,7 @@ struct vop_dump_regs {
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const char *name;
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struct vop_reg state;
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bool enable_state;
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uint32_t size;
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};
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struct vop2_vp_plane_mask {
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@@ -1315,6 +1384,11 @@ struct vop2_vp_plane_mask {
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u8 attached_layers[ROCKCHIP_MAX_LAYER];
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};
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struct vop2_esmart_lb_map {
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u8 lb_mode;
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u8 lb_map_value;
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};
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/**
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* VOP2 data structe
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*
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@@ -1337,6 +1411,8 @@ struct vop2_data {
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uint8_t nr_mem_pgs;
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uint8_t esmart_lb_mode;
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bool delayed_pd;
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uint8_t esmart_lb_mode_num;
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const struct vop2_esmart_lb_map *esmart_lb_mode_map;
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const struct vop_intr *axi_intr;
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const struct vop2_ctrl *ctrl;
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const struct vop2_dsc_data *dsc;
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@@ -1355,6 +1431,7 @@ struct vop2_data {
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const struct vop_grf_ctrl *grf;
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const struct vop_grf_ctrl *vo0_grf;
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const struct vop_grf_ctrl *vo1_grf;
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const struct vop_grf_ctrl *ioc_grf;
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const struct vop_dump_regs *dump_regs;
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uint32_t dump_regs_size;
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struct vop_rect max_input;
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@@ -1388,6 +1465,7 @@ struct vop2_data {
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#define WB_UV_FIFO_FULL_INTR BIT(17)
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#define WB_YRGB_FIFO_FULL_INTR BIT(18)
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#define WB_COMPLETE_INTR BIT(19)
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#define MMU_EN_INTR BIT(20)
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#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
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LINE_FLAG_INTR | BUS_ERROR_INTR | \
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@@ -1397,7 +1475,7 @@ struct vop2_data {
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HWC_EMPTY_INTR | \
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POST_BUF_EMPTY_INTR | \
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DMA_FINISH_INTR | FS_FIELD_INTR | \
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FE_INTR)
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FE_INTR | WB_COMPLETE_INTR | MMU_EN_INTR)
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#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
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#define FS_INTR_EN(x) ((x) << 5)
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#define LINE_FLAG_INTR_EN(x) ((x) << 6)
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@@ -1525,12 +1603,14 @@ enum vop2_scale_up_mode {
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VOP2_SCALE_UP_NRST_NBOR,
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VOP2_SCALE_UP_BIL,
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VOP2_SCALE_UP_BIC,
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VOP2_SCALE_UP_ZME,
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};
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enum vop2_scale_down_mode {
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VOP2_SCALE_DOWN_NRST_NBOR,
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VOP2_SCALE_DOWN_BIL,
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VOP2_SCALE_DOWN_AVG,
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VOP2_SCALE_DOWN_ZME,
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};
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enum vop3_pre_scale_down_mode {
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1050,9 +1050,12 @@
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#define RK3568_VOP2_GLB_CFG_DONE_EN BIT(15)
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#define RK3568_VERSION_INFO 0x004
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#define RK3568_SYS_AUTO_GATING_CTRL 0x008
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#define RK3576_SYS_MMU_CTRL_IMD 0x020
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#define RK3568_SYS_AXI_LUT_CTRL 0x024
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#define RK3568_DSP_IF_EN 0x028
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#define RK3576_SYS_PORT_CTRL_IMD 0x028
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#define RK3568_DSP_IF_CTRL 0x02c
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#define RK3576_SYS_CLUSTER_PD_CTRL_IMD 0x030
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#define RK3568_DSP_IF_POL 0x030
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#define RK3568_SYS_PD_CTRL 0x034
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#define RK3588_SYS_VAR_FREQ_CTRL 0x038
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@@ -1091,6 +1094,19 @@
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#define RK3588_VP3_INT_EN 0xD0
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#define RK3588_VP3_INT_CLR 0xD4
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#define RK3588_VP3_INT_STATUS 0xD8
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#define RK3576_WB_CTRL 0x100
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#define RK3576_WB_XSCAL_FACTOR 0x104
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#define RK3576_WB_YRGB_MST 0x108
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#define RK3576_WB_CBR_MST 0x10C
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#define RK3576_WB_VIR_STRIDE 0x110
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#define RK3576_WB_TIMEOUT_CTRL 0x114
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#define RK3576_MIPI0_IF_CTRL 0x180
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#define RK3576_HDMI0_IF_CTRL 0x184
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#define RK3576_EDP0_IF_CTRL 0x188
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#define RK3576_DP0_IF_CTRL 0x18C
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#define RK3576_RGB_IF_CTRL 0x194
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#define RK3576_DP1_IF_CTRL 0x1A4
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#define RK3576_DP2_IF_CTRL 0x1B0
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#define RK3588_DSC_8K_SYS_CTRL 0x200
|
||||
#define RK3588_DSC_8K_RST 0x204
|
||||
@@ -1202,6 +1218,8 @@
|
||||
#define RK3568_VP2_BCSH_BCS 0xE64
|
||||
#define RK3568_VP2_BCSH_H 0xE68
|
||||
#define RK3568_VP2_BCSH_COLOR_BAR 0xE6C
|
||||
#define RK3576_VP2_MCU_CTRL 0xEF8
|
||||
#define RK3576_VP2_MCU_RW_BYPASS_PORT 0xEFC
|
||||
|
||||
#define RK3588_VP3_DSP_CTRL 0xF00
|
||||
#define RK3588_VP3_DUAL_CHANNEL_CTRL 0xF04
|
||||
@@ -1238,6 +1256,10 @@
|
||||
#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
|
||||
#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
|
||||
#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
|
||||
#define RK3576_CLUSTER1_MIX_SRC_COLOR_CTRL 0x540
|
||||
#define RK3576_CLUSTER1_MIX_DST_COLOR_CTRL 0x544
|
||||
#define RK3576_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x548
|
||||
#define RK3576_CLUSTER1_MIX_DST_ALPHA_CTRL 0x54c
|
||||
#define RK3528_OVL_PORT0_CTRL 0x600
|
||||
#define RK3528_OVL_PORT0_LAYER_SEL 0x604
|
||||
#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620
|
||||
@@ -1252,6 +1274,10 @@
|
||||
#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644
|
||||
#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648
|
||||
#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C
|
||||
#define RK3576_EXTRA_SRC_COLOR_CTRL 0x650
|
||||
#define RK3576_EXTRA_DST_COLOR_CTRL 0x654
|
||||
#define RK3576_EXTRA_SRC_ALPHA_CTRL 0x658
|
||||
#define RK3576_EXTRA_DST_ALPHA_CTRL 0x65C
|
||||
#define RK3528_HDR_SRC_COLOR_CTRL 0x660
|
||||
#define RK3528_HDR_DST_COLOR_CTRL 0x664
|
||||
#define RK3528_HDR_SRC_ALPHA_CTRL 0x668
|
||||
@@ -1272,6 +1298,13 @@
|
||||
#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748
|
||||
#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C
|
||||
#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770
|
||||
#define RK3576_OVL_PORT2_CTRL 0x800
|
||||
#define RK3576_OVL_PORT2_LAYER_SEL 0x804
|
||||
#define RK3576_OVL_PORT2_MIX0_SRC_COLOR_CTRL 0x820
|
||||
#define RK3576_OVL_PORT2_MIX0_DST_COLOR_CTRL 0x824
|
||||
#define RK3576_OVL_PORT2_MIX0_SRC_ALPHA_CTRL 0x828
|
||||
#define RK3576_OVL_PORT2_MIX0_DST_ALPHA_CTRL 0x82C
|
||||
#define RK3576_OVL_PORT2_BG_MIX_CTRL 0x870
|
||||
|
||||
/* Overlay registers definition */
|
||||
#define RK3568_OVL_CTRL 0x600
|
||||
@@ -1327,6 +1360,8 @@
|
||||
#define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028
|
||||
#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_TRANSFORM_OFFSET 0x103C
|
||||
#define RK3576_CLUSTER0_WIN0_ZME_CTRL 0x1040
|
||||
#define RK3576_CLUSTER0_WIN0_ZME_DERING_PARA 0x1044
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_OUTPUT_CTRL 0x1050
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058
|
||||
@@ -1335,6 +1370,8 @@
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
|
||||
#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
|
||||
#define RK3576_CLUSTER0_WIN0_PLD_PTR_OFFSET 0x1078
|
||||
#define RK3576_CLUSTER0_WIN0_PLD_PTR_RANGE 0x107C
|
||||
|
||||
#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
|
||||
#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
|
||||
@@ -1355,8 +1392,12 @@
|
||||
#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4
|
||||
#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8
|
||||
#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC
|
||||
#define RK3576_CLUSTER0_WIN1_PLD_PTR_OFFSET 0x10F8
|
||||
#define RK3576_CLUSTER0_WIN1_PLD_PTR_RANGE 0x10FC
|
||||
|
||||
#define RK3568_CLUSTER0_CTRL 0x1100
|
||||
#define RK3576_CLUSTER0_PORT_SEL_IMD 0x11F4
|
||||
#define RK3576_CLUSTER0_DLY_NUM 0x11F8
|
||||
|
||||
#define RK3568_CLUSTER1_WIN0_CTRL0 0x1200
|
||||
#define RK3568_CLUSTER1_WIN0_CTRL1 0x1204
|
||||
@@ -1369,6 +1410,8 @@
|
||||
#define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228
|
||||
#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_TRANSFORM_OFFSET 0x123C
|
||||
#define RK3576_CLUSTER1_WIN0_ZME_CTRL 0x1240
|
||||
#define RK3576_CLUSTER1_WIN0_ZME_DERING_PARA 0x1244
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_OUTPUT_CTRL 0x1250
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258
|
||||
@@ -1377,6 +1420,8 @@
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268
|
||||
#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C
|
||||
#define RK3576_CLUSTER1_WIN0_PLD_PTR_OFFSET 0x1278
|
||||
#define RK3576_CLUSTER1_WIN0_PLD_PTR_RANGE 0x127C
|
||||
|
||||
#define RK3568_CLUSTER1_WIN1_CTRL0 0x1280
|
||||
#define RK3568_CLUSTER1_WIN1_CTRL1 0x1284
|
||||
@@ -1395,8 +1440,12 @@
|
||||
#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4
|
||||
#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8
|
||||
#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC
|
||||
#define RK3576_CLUSTER1_WIN1_PLD_PTR_OFFSET 0x12F8
|
||||
#define RK3576_CLUSTER1_WIN1_PLD_PTR_RANGE 0x12FC
|
||||
|
||||
#define RK3568_CLUSTER1_CTRL 0x1300
|
||||
#define RK3576_CLUSTER1_PORT_SEL_IMD 0x13F4
|
||||
#define RK3576_CLUSTER1_DLY_NUM 0x13F8
|
||||
|
||||
#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
|
||||
#define RK3588_CLUSTER2_WIN0_CTRL1 0x1404
|
||||
@@ -1527,6 +1576,9 @@
|
||||
#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8
|
||||
#define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC
|
||||
#define RK3568_ESMART0_COLOR_KEY_CTRL 0x18D0
|
||||
#define RK3576_ESMART0_ALPHA_MAP 0x18D8
|
||||
#define RK3576_ESMART0_PORT_SEL_IMD 0x18F4
|
||||
#define RK3576_ESMART0_DLY_NUM 0x18F8
|
||||
|
||||
#define RK3568_ESMART1_CTRL0 0x1A00
|
||||
#define RK3568_ESMART1_CTRL1 0x1A04
|
||||
@@ -1574,6 +1626,9 @@
|
||||
#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4
|
||||
#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8
|
||||
#define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC
|
||||
#define RK3576_ESMART1_ALPHA_MAP 0x1AD8
|
||||
#define RK3576_ESMART1_PORT_SEL_IMD 0x1AF4
|
||||
#define RK3576_ESMART1_DLY_NUM 0x1AF8
|
||||
|
||||
#define RK3568_SMART0_CTRL0 0x1C00
|
||||
#define RK3568_SMART0_CTRL1 0x1C04
|
||||
@@ -1621,6 +1676,9 @@
|
||||
#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4
|
||||
#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8
|
||||
#define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC
|
||||
#define RK3576_ESMART2_ALPHA_MAP 0x1CD8
|
||||
#define RK3576_ESMART2_PORT_SEL_IMD 0x1CF4
|
||||
#define RK3576_ESMART2_DLY_NUM 0x1CF8
|
||||
|
||||
#define RK3568_SMART1_CTRL0 0x1E00
|
||||
#define RK3568_SMART1_CTRL1 0x1E04
|
||||
@@ -1668,6 +1726,9 @@
|
||||
#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4
|
||||
#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
|
||||
#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
|
||||
#define RK3576_ESMART3_ALPHA_MAP 0x1ED8
|
||||
#define RK3576_ESMART3_PORT_SEL_IMD 0x1EF4
|
||||
#define RK3576_ESMART3_DLY_NUM 0x1EF8
|
||||
|
||||
/* HDR register definition */
|
||||
#define RK3568_HDR_LUT_CTRL 0x2000
|
||||
@@ -1700,11 +1761,21 @@
|
||||
#define RK3588_DSC_4K_STS0 0x41A8
|
||||
#define RK3588_DSC_4K_ERS 0x41C4
|
||||
|
||||
/* Base SYS_GRF: 0x2600a000 */
|
||||
#define RK3576_SYS_GRF_MEMFAULT_STATUS0 0x0148
|
||||
|
||||
/* Base IOC_GRF: 0x26040000 */
|
||||
#define RK3576_VCCIO_IOC_MISC_CON8 0x6420
|
||||
|
||||
/* Base PMU2: 0x27380000 */
|
||||
#define RK3576_PMU_PWR_GATE_STS 0x0230
|
||||
#define RK3576_PMU_BISR_PDGEN_CON0 0x0510
|
||||
#define RK3576_PMU_BISR_PWR_REPAIR_STATUS0 0x0570
|
||||
|
||||
#define RK3588_GRF_SOC_CON1 0x0304
|
||||
#define RK3588_GRF_VOP_CON2 0x08
|
||||
#define RK3588_GRF_VO1_CON0 0x00
|
||||
|
||||
|
||||
#define RK3588_PMU_PWR_GATE_CON1 0x150
|
||||
#define RK3588_PMU_SUBMEM_PWR_GATE_CON1 0x1B4
|
||||
#define RK3588_PMU_SUBMEM_PWR_GATE_CON2 0x1B8
|
||||
|
||||
Reference in New Issue
Block a user