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clk: rockchip: rk3588: fix up some clk parents for clk-link

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Id88179e2a852caf822f61cf79d73a4b6bbe3f893
This commit is contained in:
Elaine Zhang
2021-11-15 21:21:00 +08:00
parent 2478213d05
commit 83922fcb65
1 changed files with 64 additions and 64 deletions
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128
drivers/clk/rockchip/clk-rk3588.c
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@@ -842,12 +842,12 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(68), 0, GFLAGS),
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_root", 0,
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
RK3588_CLKGATE_CON(68), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(163), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(68), 3, GFLAGS),
GATE(PCLK_AV1, "pclk_av1", "pclk_av1_root", 0,
GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0,
RK3588_CLKGATE_CON(68), 5, GFLAGS),
/* bus */
@@ -1220,52 +1220,52 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(70), 10, GFLAGS),
/* top */
COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, 0,
COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0,
COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, 0,
COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, 0,
COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, 0,
COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, 0,
COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
@@ -1367,9 +1367,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(26), 3, GFLAGS),
GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0,
RK3588_CLKGATE_CON(26), 4, GFLAGS),
GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_root", 0,
GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0,
RK3588_CLKGATE_CON(26), 5, GFLAGS),
GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_root", 0,
GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0,
RK3588_CLKGATE_CON(26), 7, GFLAGS),
/* npu */
@@ -1425,7 +1425,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(29), 11, GFLAGS),
/* nvm */
GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0,
GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0,
RK3588_CLKGATE_CON(31), 4, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
RK3588_CLKGATE_CON(31), 5, GFLAGS),
@@ -1441,9 +1441,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS,
RK3588_CLKGATE_CON(31), 9, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm_root", 0,
GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
RK3588_CLKGATE_CON(31), 10, GFLAGS),
GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm_root", 0,
GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0,
RK3588_CLKGATE_CON(31), 11, GFLAGS),
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
@@ -1535,10 +1535,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(32), 3, GFLAGS),
GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0,
RK3588_CLKGATE_CON(32), 4, GFLAGS),
COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, 0,
COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(32), 6, GFLAGS),
COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, 0,
COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS,
RK3588_CLKGATE_CON(32), 7, GFLAGS),
GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0,
@@ -1635,9 +1635,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(40), 2, GFLAGS),
GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_root", 0,
GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0,
RK3588_CLKGATE_CON(40), 3, GFLAGS),
GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_root", 0,
GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0,
RK3588_CLKGATE_CON(40), 4, GFLAGS),
COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS,
@@ -1654,9 +1654,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(41), 1, GFLAGS),
GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_root", 0,
GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0,
RK3588_CLKGATE_CON(41), 2, GFLAGS),
GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_root", 0,
GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0,
RK3588_CLKGATE_CON(41), 3, GFLAGS),
COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS,
@@ -1672,7 +1672,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(172), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(75), 0, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_root", 0,
GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0,
RK3588_CLKGATE_CON(75), 2, GFLAGS),
COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0,
RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS,
@@ -1690,21 +1690,21 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(96), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(42), 1, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_usb_root", 0,
GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 10, GFLAGS),
GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb_root", 0,
GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 11, GFLAGS),
GATE(HCLK_HOST1, "hclk_host1", "hclk_usb_root", 0,
GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 12, GFLAGS),
GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb_root", 0,
GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0,
RK3588_CLKGATE_CON(42), 13, GFLAGS),
GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0,
GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0,
RK3588_CLKGATE_CON(42), 4, GFLAGS),
GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
RK3588_CLKGATE_CON(42), 5, GFLAGS),
GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
RK3588_CLKGATE_CON(42), 6, GFLAGS),
GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb_root", 0,
GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0,
RK3588_CLKGATE_CON(42), 7, GFLAGS),
GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
RK3588_CLKGATE_CON(42), 8, GFLAGS),
@@ -1714,28 +1714,28 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
/* vdpu */
GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 4, GFLAGS),
GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_root", 0,
GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(45), 5, GFLAGS),
COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0,
RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS,
RK3588_CLKGATE_CON(45), 6, GFLAGS),
GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_root", 0,
GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 10, GFLAGS),
GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 11, GFLAGS),
GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_root", 0,
GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 12, GFLAGS),
GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 13, GFLAGS),
GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_root", 0,
GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 14, GFLAGS),
GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 15, GFLAGS),
GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_root", 0,
GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(45), 0, GFLAGS),
GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 1, GFLAGS),
GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_root", 0,
GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0,
RK3588_CLKGATE_CON(45), 2, GFLAGS),
GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(45), 3, GFLAGS),
@@ -1765,7 +1765,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 3, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_root", 0,
GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0,
RK3588_CLKGATE_CON(44), 8, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
RK3588_CLKGATE_CON(44), 9, GFLAGS),
@@ -1790,9 +1790,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(48), 1, GFLAGS),
GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_root", 0,
GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0,
RK3588_CLKGATE_CON(48), 4, GFLAGS),
GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_root", 0,
GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0,
RK3588_CLKGATE_CON(48), 5, GFLAGS),
COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS,
@@ -1875,13 +1875,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(56), 9, GFLAGS),
GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0,
RK3588_CLKGATE_CON(55), 11, GFLAGS),
GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0,
GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0,
RK3588_CLKGATE_CON(55), 12, GFLAGS),
GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0,
GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
RK3588_CLKGATE_CON(55), 13, GFLAGS),
GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
RK3588_CLKGATE_CON(55), 14, GFLAGS),
GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0_root", 0,
GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0,
RK3588_CLKGATE_CON(56), 10, GFLAGS),
GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0,
RK3588_CLKGATE_CON(56), 0, GFLAGS),
@@ -1913,7 +1913,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_i2s4_8ch_tx_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0,
RK3588_CLKGATE_CON(56), 13, GFLAGS),
GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0_root", 0,
GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0,
RK3588_CLKGATE_CON(56), 14, GFLAGS),
COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS,
@@ -1924,7 +1924,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_i2s8_8ch_tx_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0,
RK3588_CLKGATE_CON(57), 1, GFLAGS),
GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0_root", 0,
GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0,
RK3588_CLKGATE_CON(57), 2, GFLAGS),
COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS,
@@ -1937,7 +1937,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(57), 5, GFLAGS),
GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0,
RK3588_CLKGATE_CON(57), 6, GFLAGS),
GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0_root", 0,
GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0,
RK3588_CLKGATE_CON(57), 7, GFLAGS),
COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS,
@@ -1974,9 +1974,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(62), 5, GFLAGS),
GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(60), 4, GFLAGS),
GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_root", 0,
GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0,
RK3588_CLKGATE_CON(60), 5, GFLAGS),
GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0,
GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
RK3588_CLKGATE_CON(60), 6, GFLAGS),
GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
RK3588_CLKGATE_CON(60), 7, GFLAGS),
@@ -2042,7 +2042,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(59), 15, GFLAGS),
GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0,
RK3588_CLKGATE_CON(65), 8, GFLAGS),
GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1_root", 0,
GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(65), 4, GFLAGS),
COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS,
@@ -2053,7 +2053,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_i2s10_8ch_rx_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0,
RK3588_CLKGATE_CON(65), 7, GFLAGS),
GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1_root", 0,
GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(60), 0, GFLAGS),
COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS,
@@ -2064,7 +2064,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_i2s7_8ch_rx_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0,
RK3588_CLKGATE_CON(60), 3, GFLAGS),
GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1_root", 0,
GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(65), 0, GFLAGS),
COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS,
@@ -2084,7 +2084,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_i2s5_8ch_tx_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0,
RK3588_CLKGATE_CON(62), 8, GFLAGS),
GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1_root", 0,
GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(62), 12, GFLAGS),
COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS,
@@ -2106,9 +2106,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(63), 2, GFLAGS),
MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT,
RK3588_CLKSEL_CON(148), 2, 2, MFLAGS),
GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1_root", 0,
GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 3, GFLAGS),
GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1_root", 0,
GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 4, GFLAGS),
COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS,
@@ -2119,7 +2119,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_spdif3_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0,
RK3588_CLKGATE_CON(63), 7, GFLAGS),
GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1_root", 0,
GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 8, GFLAGS),
COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0,
RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS,
@@ -2130,25 +2130,25 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
&rk3588_spdif4_fracmux, RK3588_FRAC_MAX_PRATE),
GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0,
RK3588_CLKGATE_CON(63), 11, GFLAGS),
GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1_root", 0,
GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 12, GFLAGS),
COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 13, GFLAGS),
GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1_root", 0,
GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
RK3588_CLKGATE_CON(63), 14, GFLAGS),
COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(63), 15, GFLAGS),
GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1_root", 0,
GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0,
RK3588_CLKGATE_CON(64), 0, GFLAGS),
COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0,
RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(64), 1, GFLAGS),
COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, 0,
COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(74), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
RK3588_CLKSEL_CON(170), 6, 2, MFLAGS,
RK3588_CLKGATE_CON(74), 2, GFLAGS),
GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,