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ARM: dts: rockchip: rk3288 fix cpu opp table
Change-Id: If8831cb6b23c95d48b3f2f046f766e3f9f42dc2b Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
@@ -7,7 +7,6 @@
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/suspend/rockchip-rk3288.h>
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@@ -65,7 +64,7 @@
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resets = <&cru SRST_CORE0>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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dynamic-power-coefficient = <322>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@501 {
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@@ -74,9 +73,6 @@
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reg = <0x501>;
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resets = <&cru SRST_CORE1>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu2: cpu@502 {
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device_type = "cpu";
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@@ -84,9 +80,6 @@
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reg = <0x502>;
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resets = <&cru SRST_CORE2>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu3: cpu@503 {
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device_type = "cpu";
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@@ -94,66 +87,143 @@
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reg = <0x503>;
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resets = <&cru SRST_CORE3>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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};
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cpu_opp_table: cpu-opp-table {
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cpu_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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nvmem-cells = <&cpu_leakage>;
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nvmem-cell-names = "cpu_leakage";
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clocks = <&cru PLL_APLL>;
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rockchip,avs-scale = <17>;
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rockchip,max-volt = <1350000>;
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nvmem-cells = <&cpu_leakage>, <&special_function>,
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<&performance>, <&process_version>,
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<&performance_w>, <&package_info>;
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nvmem-cell-names = "leakage", "special",
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"performance", "process",
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"performance-w", "package";
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rockchip,bin-scaling-sel = <
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0 17
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1 25
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2 27
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3 31
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>;
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rockchip,pvtm-voltage-sel = <
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0 14300 0
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14301 15000 1
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15001 16000 2
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16001 99999 3
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>;
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rockchip,pvtm-freq = <408000>;
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rockchip,pvtm-volt = <1000000>;
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rockchip,pvtm-ch = <0 0>;
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rockchip,pvtm-sample-time = <1000>;
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rockchip,pvtm-number = <10>;
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rockchip,pvtm-error = <1000>;
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rockchip,pvtm-ref-temp = <35>;
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rockchip,pvtm-temp-prop = <(-18) (-18)>;
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rockchip,thermal-zone = "soc-thermal";
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opp-126000000 {
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opp-hz = /bits/ 64 <126000000>;
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opp-microvolt = <900000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <950000 950000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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opp-microvolt-L3 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-216000000 {
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opp-hz = /bits/ 64 <216000000>;
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opp-microvolt = <900000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <900000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <950000 950000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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opp-microvolt-L3 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000>;
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opp-microvolt = <975000 975000 1350000>;
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opp-microvolt-L0 = <975000 975000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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opp-microvolt-L3 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000>;
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opp-microvolt = <975000 975000 1350000>;
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opp-microvolt-L0 = <975000 975000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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opp-microvolt-L3 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-696000000 {
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opp-hz = /bits/ 64 <696000000>;
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opp-microvolt = <950000>;
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opp-microvolt = <975000 975000 1350000>;
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opp-microvolt-L0 = <975000 975000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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opp-microvolt-L3 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1000000>;
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opp-microvolt = <1075000 1075000 1350000>;
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opp-microvolt-L0 = <1075000 1075000 1350000>;
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opp-microvolt-L1 = <1050000 1050000 1350000>;
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opp-microvolt-L2 = <1000000 1000000 1350000>;
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opp-microvolt-L3 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1050000>;
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opp-microvolt = <1150000 1150000 1350000>;
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opp-microvolt-L0 = <1150000 1150000 1350000>;
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opp-microvolt-L1 = <1100000 1100000 1350000>;
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opp-microvolt-L2 = <1050000 1050000 1350000>;
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opp-microvolt-L3 = <1000000 1000000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1100000>;
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opp-microvolt = <1200000 1200000 1350000>;
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opp-microvolt-L0 = <1200000 1200000 1350000>;
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opp-microvolt-L1 = <1150000 1150000 1350000>;
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opp-microvolt-L2 = <1100000 1100000 1350000>;
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opp-microvolt-L3 = <1050000 1050000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <1200000>;
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opp-microvolt = <1300000 1300000 1350000>;
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opp-microvolt-L0 = <1300000 1300000 1350000>;
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opp-microvolt-L1 = <1250000 1250000 1350000>;
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opp-microvolt-L2 = <1200000 1200000 1350000>;
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opp-microvolt-L3 = <1150000 1150000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1512000000 {
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opp-hz = /bits/ 64 <1512000000>;
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opp-microvolt = <1300000>;
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opp-microvolt = <1350000 1350000 1350000>;
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opp-microvolt-L0 = <1350000 1350000 1350000>;
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opp-microvolt-L1 = <1300000 1300000 1350000>;
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opp-microvolt-L2 = <1250000 1250000 1350000>;
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opp-microvolt-L3 = <1200000 1200000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1350000>;
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opp-microvolt = <1350000 1350000 1350000>;
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opp-microvolt-L0 = <1350000 1350000 1350000>;
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opp-microvolt-L1 = <1350000 1350000 1350000>;
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opp-microvolt-L2 = <1300000 1300000 1350000>;
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opp-microvolt-L3 = <1250000 1250000 1350000>;
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clock-latency-ns = <40000>;
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};
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};
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@@ -239,14 +309,6 @@
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arm,no-tick-in-suspend;
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};
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timer: timer@ff810000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0x0 0xff810000 0x0 0x20>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vopl_out>, <&vopb_out>;
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@@ -496,28 +558,21 @@
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status = "disabled";
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};
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thermal-zones {
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reserve_thermal: reserve_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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thermal-sensors = <&tsadc 0>;
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};
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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thermal_zones: thermal-zones {
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cpu_thermal: soc-thermal {
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polling-delay-passive = <200>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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sustainable-power = <1200>; /* milliwatts */
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thermal-sensors = <&tsadc 1>;
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trips {
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cpu_alert0: cpu_alert0 {
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temperature = <70000>; /* millicelsius */
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cpu_alert0: trip-point@0 {
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temperature = <75000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert1: cpu_alert1 {
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temperature = <75000>; /* millicelsius */
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cpu_alert1: trip-point@1 {
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temperature = <85000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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@@ -530,44 +585,24 @@
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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trip = <&cpu_alert1>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT 6>;
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <1024>;
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};
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};
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};
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gpu_thermal: gpu_thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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gpu_thermal: gpu-thermal {
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polling-delay-passive = <200>; /* milliseconds */
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polling-delay = <1000>; /* milliseconds */
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thermal-sensors = <&tsadc 2>;
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trips {
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gpu_alert0: gpu_alert0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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gpu_crit: gpu_crit {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&gpu_alert0>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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@@ -752,6 +787,14 @@
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status = "disabled";
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};
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timer: timer@ff6b0000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0x0 0xff6b0000 0x0 0x20>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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bus_intmem@ff700000 {
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compatible = "mmio-sram";
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reg = <0x0 0xff700000 0x0 0x18000>;
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@@ -1100,6 +1143,15 @@
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reset-names = "phy-reset";
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};
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};
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pvtm: pvtm {
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compatible = "rockchip,rk3288-pvtm";
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clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
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clock-names = "core", "gpu";
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resets = <&cru SRST_CORE_PVTM>, <&cru SRST_GPU_PVTM>;
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reset-names = "core", "gpu";
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status = "okay";
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};
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};
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wdt: watchdog@ff800000 {
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