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ethernet: fix wol_error when test eye_pattern
PD#166642: add eye pattern function for 4.9 Change-Id: If57f74262589c02e12cbff3f01745c70a687da9e Signed-off-by: Zhuo Wang <zhuo.wang@amlogic.com>
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@@ -126,6 +126,7 @@ void reset_internal_phy(struct phy_device *phydev)
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pr_info("reset phy\n");
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}
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unsigned int enable_wol_check = 1;
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static int internal_phy_read_status(struct phy_device *phydev)
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{
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int err;
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@@ -142,22 +143,28 @@ static int internal_phy_read_status(struct phy_device *phydev)
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/*Bit 9:5: Read Address*/
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/*Bit 4:0: Write Address*/
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/*read wol bank reg12*/
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val = ((1 << 15) | (1 << 11) | (1 << 10) | (12 << 5));
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phy_write(phydev, 0x14, val);
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wol_reg12 = phy_read(phydev, 0x15);
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if ((phydev->link) && (phydev->speed != SPEED_10)) {
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if ((wol_reg12 & 0x1000))
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/*add enable/disable to stop the check for debug*/
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/*cause this part will involve many issue*/
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if (enable_wol_check) {
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val = ((1 << 15) | (1 << 11) | (1 << 10) | (12 << 5));
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phy_write(phydev, 0x14, val);
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wol_reg12 = phy_read(phydev, 0x15);
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if ((phydev->link) && (phydev->speed != SPEED_10)) {
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if ((wol_reg12 & 0x1000))
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reg12_error_count = 0;
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if (!(wol_reg12 & 0x1000)) {
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reg12_error_count++;
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pr_info("wol_reg12[12]==0, error\n");
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}
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if (reg12_error_count >=
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(phydev->drv->features & 0xff)) {
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reg12_error_count = 0;
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reset_internal_phy(phydev);
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}
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} else {
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reg12_error_count = 0;
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if (!(wol_reg12 & 0x1000)) {
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reg12_error_count++;
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pr_info("wol_reg12[12]==0, error\n");
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}
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if (reg12_error_count >= (phydev->drv->features & 0xff)) {
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reg12_error_count = 0;
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reset_internal_phy(phydev);
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}
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} else {
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reg12_error_count = 0;
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}
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linkup = phydev->link;
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err = genphy_update_link(phydev);
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@@ -553,6 +553,8 @@ static void am_net_eye_pattern_on(void)
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unsigned int value;
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c_phy_dev->autoneg = AUTONEG_DISABLE;
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/*stop check wol when doing eye pattern, otherwise it will reset phy*/
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enable_wol_check = 0;
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phy_write(c_phy_dev, 0, 0x2100);
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value = phy_read(c_phy_dev, 17);
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pr_info("0x11 %x\n", value);
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@@ -563,12 +565,20 @@ static void am_net_eye_pattern_off(void)
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unsigned int value;
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c_phy_dev->autoneg = AUTONEG_ENABLE;
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enable_wol_check = 1;
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phy_write(c_phy_dev, 0, 0x1000);
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value = phy_read(c_phy_dev, 17);
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pr_info("0x11 %x\n", value);
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phy_write(c_phy_dev, 17, (value & ~0x0004));
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}
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static void am_net_debug_mode(void)
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{ /*disable autoneg*/
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c_phy_dev->autoneg = AUTONEG_DISABLE;
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/*disable wol check*/
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enable_wol_check = 0;
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}
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static ssize_t eth_phyreg_func(
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struct class *class, struct class_attribute *attr,
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const char *buf, size_t count)
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@@ -642,6 +652,10 @@ static ssize_t eth_phyreg_func(
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am_net_eye_pattern_off();
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break;
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}
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if (argv[0][1] == 'd' || argv[0][1] == 'D') {
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am_net_debug_mode();
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break;
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}
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break;
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default:
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goto end;
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@@ -36,7 +36,8 @@
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#include <linux/net_tstamp.h>
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#include "eth_reg.h"
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/*add this to stop checking wol,which will reset phy*/
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extern unsigned int enable_wol_check;
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int gmac_create_sysfs(struct phy_device *phydev, void __iomem *ioaddr);
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int gmac_remove_sysfs(struct phy_device *phydev);
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#endif
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