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hdmirx: optimizing rx fsm for tl1 [1/1]

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PD#172587

Problem:
1.optimizing rx fsm for tl1, some time cable
clk not stable

Solution:
1.use system clk measure
2.modify low frq phy and pll setting
3.fsm stable state add error cnt check

Verify:
tl1

Change-Id: I6b9078bdf73fc0a2269ed9386fd42db0678cf995
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2018-11-19 11:20:04 +08:00
committed by Bo Yang
parent 8f714e0c7b
commit 84489b05e8
5 changed files with 194 additions and 117 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -41,7 +41,7 @@
*
*
*/
#define RX_VER1 "ver.2018/10/22"
#define RX_VER1 "ver.2018/11/20"
/*
*
*

219
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -2148,7 +2148,7 @@ void hdmirx_phy_init(void)
data32 |= rx.port << 2;
hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32);
cur_cable_clk = rx_get_clock(TOP_HDMI_CABLECLK);
cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);
data32 = rx_get_scdc_clkrate_sts();
if (cur_cable_clk > 0)
aml_phy_bw_switch(cur_cable_clk, data32);
@@ -3158,11 +3158,11 @@ int rx_get_aud_pll_err_sts(void)
return ret;
}
unsigned int aml_check_clk_bandwidth(unsigned int cableclk,
unsigned int clkrate)
uint32_t aml_cable_clk_band(uint32_t cableclk,
uint32_t clkrate)
{
unsigned int bw;
unsigned int cab_clk = cableclk;
uint32_t bw;
uint32_t cab_clk = cableclk;
/*rx_pr("cable clk=%d, clkrate=%d\n", cableclk, clkrate);*/
/* 1:40 */
@@ -3170,33 +3170,33 @@ unsigned int aml_check_clk_bandwidth(unsigned int cableclk,
cab_clk = cableclk << 2;
/* 1:10 */
if (cab_clk < (40 * MHz))
bw = apll_bw_24_40;
else if (cab_clk < (80 * MHz))
bw = apll_bw_40_80;
else if (cab_clk < (150 * MHz))
bw = apll_bw_80_150;
else if (cab_clk < (300 * MHz))
bw = apll_bw_150_300;
else if (cab_clk < (600 * MHz))
bw = apll_bw_300_600;
if (cab_clk < (45*MHz))
bw = phy_frq_band_0;
else if (cab_clk < (77*MHz))
bw = phy_frq_band_1;
else if (cab_clk < (155*MHz))
bw = phy_frq_band_2;
else if (cab_clk < (300*MHz))
bw = phy_frq_band_3;
else if (cab_clk < (600*MHz))
bw = phy_frq_band_4;
else {
bw = apll_bw_80_150;
bw = phy_frq_band_2;
rx_pr("phy err: bw clk=%d\n", cableclk);
}
return bw;
}
void aml_phy_init(unsigned int bw)
void aml_phy_init(uint32_t bw)
{
unsigned int data32;
unsigned int term_value = 0x7;/*all terminal on*/
uint32_t data32;
uint32_t term_value = 0x7;/*all terminal on*/
/* hdmirx_rd_top(TOP_HPD_PWR5V);*/
rx_pr("init phy port %d, bw:%d\n", rx.port, bw);
if (bw == apll_bw_null) {
if (bw == phy_frq_null) {
return;
} else if (bw <= apll_bw_24_40) {
} else if (bw <= phy_frq_band_0) {
/* enable terminal connect */
data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);/*35c*/
@@ -3205,7 +3205,7 @@ void aml_phy_init(unsigned int bw)
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);/*35c*/
rx_pr("MISC_CNTL0=0x%x\n", data32);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);/*360*/
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);/*380*/
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000);/*380*/
/* reset and select data port */
data32 = 0x00000010;
data32 |= ((1 << rx.port) << 6);
@@ -3218,10 +3218,11 @@ void aml_phy_init(unsigned int bw)
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000182);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x2800c202);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x010088a2);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c714a);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e013130);
} else if (bw <= apll_bw_40_80) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e413130);
} else if (bw <= phy_frq_band_1) {
/* enable terminal connect */
data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);/*35c*/
@@ -3247,7 +3248,7 @@ void aml_phy_init(unsigned int bw)
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000);/*39c*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e062620);/*398*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e462620);/*398*/
} else if (bw <= apll_bw_80_150) {
} else if (bw <= phy_frq_band_2) {
/* enable terminal connect */
data32 = 0x30034078|(term_value & 0x7);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);/*35c*/
@@ -3272,7 +3273,7 @@ void aml_phy_init(unsigned int bw)
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000);/*39c*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e062620);/*398*/
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e462620);/*398*/
} else if (bw <= apll_bw_150_300) {
} else if (bw <= phy_frq_band_3) {
/* 3G */
/* enable terminal connect */
data32 = 0x30034078|(term_value & 0x7);
@@ -3328,19 +3329,18 @@ void aml_phy_init(unsigned int bw)
}
}
void aml_eq_setting(unsigned int bw)
void aml_eq_setting(uint32_t bw)
{
static uint32_t cnt;
if (bw == apll_bw_null) {
if (bw == phy_frq_null) {
return;
} else if (bw <= apll_bw_24_40) {
} else if (bw <= phy_frq_band_0) {
#if 0
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e013130);
#endif
} else if (bw <= apll_bw_40_80) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e413130);
#else
if (cnt & 0x1) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e022220);
@@ -3352,7 +3352,20 @@ void aml_eq_setting(unsigned int bw)
udelay(1);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e462620);
}
} else if (bw <= apll_bw_80_150) {
#endif
} else if (bw <= phy_frq_band_1) {
if (cnt & 0x1) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e022220);
udelay(1);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e422220);
} else {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e062620);
udelay(1);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e462620);
}
} else if (bw <= phy_frq_band_2) {
if (cnt & 0x1) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e022220);
@@ -3364,7 +3377,7 @@ void aml_eq_setting(unsigned int bw)
udelay(1);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e462620);
}
} else if (bw <= apll_bw_150_300) {
} else if (bw <= phy_frq_band_3) {
if (cnt & 0x1) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e022220);
@@ -3392,29 +3405,58 @@ void aml_eq_setting(unsigned int bw)
struct apll_param apll_tab[] = {
/*od for tmds: 2/4/8/16/32*/
/*od2 for audio: 1/2/4/8/16*/
/* bw M, N, od, od_div, od2, od2_div */
{apll_bw_24_40, 160, 1, 0x5, 32, 0x3, 8},/*tmdsx4*/
{apll_bw_40_80, 80, 1, 0x4, 16, 0x3, 8},/*tmdsx2*/
{apll_bw_80_150, 40, 1, 0x3, 8, 0x3, 8},/*tmds*/
{apll_bw_150_300, 40, 2, 0x2, 4, 0x2, 4},/*tmds*/
{apll_bw_300_600, 40, 1, 0x1, 2, 0x1, 2},/*tmds*/
{apll_bw_null, 40, 1, 0x3, 8, 0x3, 8},
/* bw M, N, od, od_div, od2, od2_div */
{pll_frq_band_0, 160, 1, 0x5, 32, 0x3, 8},/*tmdsx4*/
{pll_frq_band_1, 80, 1, 0x4, 16, 0x3, 8},/*tmdsx2*/
{pll_frq_band_2, 40, 1, 0x3, 8, 0x3, 8},/*tmds*/
{pll_frq_band_3, 40, 2, 0x2, 4, 0x2, 4},/*tmds*/
{pll_frq_band_4, 40, 1, 0x1, 2, 0x1, 2},/*tmds*/
{pll_frq_null, 40, 1, 0x3, 8, 0x3, 8},
};
void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
uint32_t aml_phy_pll_band(uint32_t cableclk,
uint32_t clkrate)
{
unsigned int M, N;
unsigned int od, od_div;
unsigned int od2, od2_div;
unsigned int bw = bandwidth;
unsigned int vco_clk;
unsigned int apll_out;
unsigned int aud_pll_out;
unsigned int data, data2;
unsigned int aud_div;
unsigned int cableclk = cable_clk / KHz;
uint32_t bw;
uint32_t cab_clk = cableclk;
rx_pr("bw:%d, cableclk:%d\n", bandwidth, cableclk);
if (clkrate)
cab_clk = cableclk << 2;
/* 1:10 */
if (cab_clk < (35*MHz))
bw = pll_frq_band_0;
else if (cab_clk < (77*MHz))
bw = pll_frq_band_1;
else if (cab_clk < (155*MHz))
bw = pll_frq_band_2;
else if (cab_clk < (300*MHz))
bw = pll_frq_band_3;
else if (cab_clk < (600*MHz))
bw = pll_frq_band_4;
else {
bw = pll_frq_band_2;
rx_pr("phy err: bw clk=%d\n", cableclk);
}
return bw;
}
void aml_phy_pll_setting(uint32_t cable_clk, uint32_t clkrate)
{
uint32_t M, N;
uint32_t od, od_div;
uint32_t od2, od2_div;
uint32_t bw;
uint32_t vco_clk;
uint32_t apll_out;
uint32_t aud_pll_out;
uint32_t data, data2;
uint32_t aud_div;
uint32_t cableclk = cable_clk / KHz;
bw = aml_phy_pll_band(cable_clk, clkrate);
rx_pr("bw:%d, cableclk:%d\n", bw, cableclk);
od_div = apll_tab[bw].od_div;
od = apll_tab[bw].od;
M = apll_tab[bw].M;
@@ -3428,9 +3470,9 @@ void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
/*tmds clk out*/
apll_out = (vco_clk/od_div)/5;
rx_pr("M=%d,N=%d,od=%d,od_div=%d\n", M, N, od, od_div);
/*rx_pr("M=%d,N=%d,od=%d,od_div=%d\n", M, N, od, od_div);*/
rx_pr("apll_out=%d, vco_clk=%d\n", apll_out, vco_clk);
rx_pr("od2=%d, od2_div=%d\n", od2, od2_div);
/*rx_pr("od2=%d, od2_div=%d\n", od2, od2_div);*/
aud_pll_out = ((vco_clk/od2_div)/5);
rx_pr("aud pll out=%d\n", aud_pll_out);
@@ -3442,9 +3484,14 @@ void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x20000000);
udelay(2);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x30000000);
rx_pr("APLL_CNTL0:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));
/*rx_pr("APLL_CNTL0:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));*/
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0);
udelay(50);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL1, 0x00000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001108);
if (bw <= pll_frq_band_1)
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000110e);
else
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001108);
data2 = 0x10058f30|od2;
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL3, data2);
@@ -3454,20 +3501,19 @@ void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
udelay(2);
/*apll_vctrl_mon_en*/
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2|0x00800000);
rx_pr("APLL_CNTL4:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL4));
/*rx_pr("APLL_CNTL4:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL4));*/
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL4);
udelay(80);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000);
udelay(2);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000);
rx_pr("APLL_CNTL0:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00003008);
/*wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000);*/
/*wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e040400);*/
/*udelay(2);*/
/*wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e440400);*/
/*rx_pr("APLL_CNTL0:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));*/
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0);
udelay(60);
if (bw <= pll_frq_band_1)
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000300e);
else
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00003008);
/* common block release reset */
data = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
data &= ~(0x7 << 7);
@@ -3479,7 +3525,7 @@ void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
/*set audio pll divider*/
aud_div = aud_pll_out/apll_out;
rx_pr("aud div=%d\n", aud_div);
/*rx_pr("aud div=%d\n", aud_div);*/
if (aud_div == 1)
data = 0;
else if (aud_div == 2)
@@ -3493,9 +3539,9 @@ void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cable_clk)
rx.physts.aud_div = data;
}
void aml_phy_pw_onoff(unsigned int onoff)
void aml_phy_pw_onoff(uint32_t onoff)
{
unsigned int data = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0);
uint32_t data = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0);
if (onoff) {
/* apll power down */
@@ -3511,22 +3557,24 @@ void aml_phy_pw_onoff(unsigned int onoff)
data &= ~(1 << 9);
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data);
} else {
aml_phy_init(apll_bw_80_150);
/*tl1_apll_setting(apll_bw_80_150);*/
aml_phy_init(phy_frq_band_2);
/*tl1_apll_setting(apll_frq_band_2);*/
}
}
/*
* aml phy initial
*/
void aml_phy_bw_switch(unsigned int cableclk, unsigned int clkrate)
void aml_phy_bw_switch(uint32_t cableclk, uint32_t clkrate)
{
unsigned int bw;
uint32_t bw;
bw = aml_check_clk_bandwidth(cableclk, clkrate);
if (cableclk == 0)
cableclk = PHY_DEFAULT_FRQ;
bw = aml_cable_clk_band(cableclk, clkrate);
aml_phy_init(bw);
udelay(1);
aml_phy_pll_setting(bw, cableclk);
aml_phy_pll_setting(cableclk, clkrate);
udelay(1);
aml_eq_setting(bw);
}
@@ -3541,20 +3589,29 @@ unsigned int aml_phy_pll_lock(void)
unsigned int aml_phy_tmds_valid(void)
{
unsigned int tmvds_valid;
unsigned int tmds_valid;
unsigned int sqofclk;
unsigned int pll_lock;
unsigned int tmds_align;
tmvds_valid = hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 0x01;
tmds_valid = hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 0x01;
sqofclk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
pll_lock = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000;
tmds_align = hdmirx_rd_top(TOP_TMDS_ALIGN_STAT) & 0x3f000000;
if (tmvds_valid && sqofclk && pll_lock &&
if (tmds_valid && sqofclk && pll_lock &&
(tmds_align == 0x3f000000))
return true;
else
else {
if (log_level & VIDEO_LOG) {
rx_pr("tmds:%x,sqo:%x,lock:%x,align:%x\n",
tmds_valid, sqofclk, pll_lock, tmds_align);
rx_pr("cable clk0:%d\n",
rx_measure_clock(MEASURE_CLK_CABLE));
rx_pr("cable clk1:%d\n",
rx_get_clock(TOP_HDMI_CABLECLK));
}
return false;
}
}
void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2)

37
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -1227,15 +1227,23 @@ enum measure_clk_src_e {
#define PHY_DEFAULT_FRQ ((100)*MHz)
enum apllbw {
apll_bw_24_40 = 0,
apll_bw_40_80,
apll_bw_80_150,
apll_bw_150_300,
apll_bw_300_600,
apll_bw_null = 0xf,
enum phy_frq_band {
phy_frq_band_0 = 0,
phy_frq_band_1,
phy_frq_band_2,
phy_frq_band_3,
phy_frq_band_4,
phy_frq_null = 0xf,
};
enum pll_frq_band {
pll_frq_band_0 = 0,
pll_frq_band_1,
pll_frq_band_2,
pll_frq_band_3,
pll_frq_band_4,
pll_frq_null = 0xf,
};
struct apll_param {
unsigned int bw;
@@ -1250,15 +1258,16 @@ struct apll_param {
extern int rx_get_clock(enum measure_clk_top_e clk_src);
extern unsigned int clk_util_clk_msr(unsigned int clk_mux);
extern unsigned int rx_measure_clock(enum measure_clk_src_e clksrc);
extern void aml_phy_init(unsigned int bw);
extern void aml_phy_pw_onoff(unsigned int onoff);
extern unsigned int aml_check_clk_bandwidth(unsigned int cableclk,
unsigned int clkrate);
extern void aml_sw_apll(unsigned int bandwidth, unsigned int cableclk);
extern void aml_phy_bw_switch(unsigned int cableclk, unsigned int clkrate);
extern void aml_phy_init(uint32_t bw);
extern void aml_phy_pw_onoff(uint32_t onoff);
extern uint32_t aml_cable_clk_band(uint32_t cableclk,
uint32_t clkrate);
extern uint32_t aml_phy_pll_band(uint32_t cableclk,
uint32_t clkrate);
extern void aml_phy_bw_switch(uint32_t cableclk, uint32_t clkrate);
extern unsigned int aml_phy_pll_lock(void);
extern unsigned int aml_phy_tmds_valid(void);
extern void aml_eq_setting(unsigned int bw);
extern void aml_eq_setting(uint32_t bw);
extern void rx_emp_to_ddr_init(void);
extern void rx_emp_field_done_irq(void);
extern void rx_emp_status(void);

52
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -57,6 +57,10 @@ static int dwc_rst_wait_cnt_max = 1;
static int sig_stable_cnt;
static int sig_stable_max = 10;
static int sig_stable_err_cnt;
static int sig_stable_err_max = 5;
static int max_err_cnt = 10;
static bool clk_debug;
static int hpd_wait_cnt;
@@ -983,6 +987,7 @@ bool rx_is_nosig(void)
static bool rx_is_timing_stable(void)
{
bool ret = true;
uint32_t ch0 = 0, ch1 = 0, ch2 = 0;
if ((abs(rx.cur.hactive - rx.pre.hactive) > diff_pixel_th) &&
(stable_check_lvl & HACTIVE_EN)) {
@@ -1065,6 +1070,22 @@ static bool rx_is_timing_stable(void)
rx.pre.colordepth,
rx.cur.colordepth);
}
/*for aml phy, check error counter*/
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1 &&
(stable_check_lvl & ERR_CNT_EN)) {
rx_get_error_cnt(&ch0, &ch1, &ch2);
if ((ch0 + ch1 + ch2) > max_err_cnt) {
if (sig_stable_err_cnt++ > sig_stable_err_max) {
rx_pr("warning: more err counter\n");
sig_stable_err_cnt = 0;
/*phy setting is fail, need reset phy*/
sig_unstable_cnt = sig_unstable_max;
rx.physts.cable_clk = 0;
}
ret = false;
}
}
if ((ret == false) && (log_level & VIDEO_LOG))
rx_pr("\n");
@@ -2012,21 +2033,17 @@ void rx_5v_monitor(void)
*/
void rx_clk_rate_monitor(void)
{
int cur_cable_clk;
int cur_cable_clk/*, cur_cable_clk1*/;
unsigned int clk_diff;
unsigned int cur_phy_bw, i = 0;
static unsigned int phy_bw_cnt;
unsigned int cur_clk_rate;
unsigned int pll_lock = 0;
/*cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);*/
cur_cable_clk = rx_get_clock(TOP_HDMI_CABLECLK);
if (cur_cable_clk < 0)
return;
cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);
clk_diff = diff(rx.physts.cable_clk, cur_cable_clk);
cur_clk_rate = rx_get_scdc_clkrate_sts();
cur_phy_bw = aml_check_clk_bandwidth(cur_cable_clk, cur_clk_rate);
cur_phy_bw = aml_cable_clk_band(cur_cable_clk, cur_clk_rate);
if ((rx.cur_5v_sts) && ((rx.physts.phy_bw != cur_phy_bw) ||
(rx.physts.clk_rate != cur_clk_rate) ||
(clk_diff > (1000*KHz)))) {
@@ -2037,8 +2054,8 @@ void rx_clk_rate_monitor(void)
i, cur_cable_clk, cur_clk_rate);
aml_phy_bw_switch(cur_cable_clk, cur_clk_rate);
udelay(50);/*wait pll lock*/
if ((cur_cable_clk < (20 * MHz)) ||
aml_phy_pll_lock())
pll_lock = aml_phy_pll_lock();
if ((cur_cable_clk < (20 * MHz)) || pll_lock)
break;
}
rx.physts.cable_clk = cur_cable_clk;
@@ -2071,6 +2088,7 @@ void rx_monitor_error_counter(void)
return;
timestap = get_seconds();
if ((timestap - rx.physts.timestap) > 1) {
rx.physts.timestap = timestap;
rx_get_error_cnt(&ch0, &ch1, &ch2);
@@ -2162,7 +2180,6 @@ char *fsm_st[] = {
void rx_main_state_machine(void)
{
int pre_auds_ch_alloc;
uint32_t ch0, ch1, ch2;
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1)
rx_clk_rate_monitor();
@@ -2298,6 +2315,7 @@ void rx_main_state_machine(void)
dwc_rst_wait_cnt = 0;
sig_stable_cnt = 0;
sig_unstable_cnt = 0;
sig_stable_err_cnt = 0;
rx.state = FSM_SIG_STABLE;
break;
case FSM_SIG_STABLE:
@@ -2332,16 +2350,6 @@ void rx_main_state_machine(void)
dvi_check_en = false;
break;
}
if (rx.hdmirxdev->data->chip_id
== CHIP_ID_TL1) {
rx_get_error_cnt(&ch0, &ch1, &ch2);
if (ch0 || ch1 || ch2) {
rx_pr("have err cnt\n");
aml_phy_bw_switch(
rx.physts.cable_clk,
rx.physts.clk_rate);
}
}
rx.skip = 0;
rx.state = FSM_SIG_READY;
rx.aud_sr_stable_cnt = 0;
@@ -2362,6 +2370,7 @@ void rx_main_state_machine(void)
#ifdef K_TEST_CHK_ERR_CNT
rx_monitor_error_cnt_start();
#endif
sig_stable_err_cnt = 0;
}
} else {
sig_stable_cnt = 0;
@@ -2973,6 +2982,7 @@ static void dump_phy_status(void)
rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0));
rx_pr("TMDS_ALIGN_STAT = 0x%x\n",
hdmirx_rd_top(TOP_TMDS_ALIGN_STAT));
rx_pr("all valid = 0x%x\n", aml_phy_tmds_valid());
}
}

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h
View File

@@ -30,6 +30,7 @@
#define INTERLACED_EN 0x100
#define HDCP_ENC_EN 0x200
#define COLOR_DEP_EN 0x400
#define ERR_CNT_EN 0x800
/* aud sample rate stable range */
/* #define AUD_SR_RANGE 2000 */