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Merge branch 'rk3399_android' of ssh://git.linuxfactory.or.kr:29418/people/luke/rk3399/kernel into HEAD

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Change-Id: Ia5db9d9b7aca95d888bd8d85ceace012e8512604
This commit is contained in:
Luke Go
2018-01-30 09:01:33 +09:00
parent dd1ab3a9ba 8fefd6290c
commit 84640a73ec
5051 changed files with 1570832 additions and 273799 deletions
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2
Documentation/00-INDEX
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@@ -435,6 +435,8 @@ sysrq.txt
- info on the magic SysRq key.
target/
- directory with info on generating TCM v4 fabric .ko modules
tee.txt
- info on the TEE subsystem and drivers
this_cpu_ops.txt
- List rationale behind and the way to use this_cpu operations.
thermal/

59
Documentation/DocBook/gpu.tmpl
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@@ -2543,7 +2543,7 @@ void intel_crt_init(struct drm_device *dev)
<td valign="top" >Description/Restrictions</td>
</tr>
<tr>
<td rowspan="37" valign="top" >DRM</td>
<td rowspan="42" valign="top" >DRM</td>
<td valign="top" >Generic</td>
<td valign="top" >“rotation”</td>
<td valign="top" >BITMASK</td>
@@ -2795,7 +2795,7 @@ void intel_crt_init(struct drm_device *dev)
<td valign="top" >property to suggest an Y offset for a connector</td>
</tr>
<tr>
<td rowspan="3" valign="top" >Optional</td>
<td rowspan="8" valign="top" >Optional</td>
<td valign="top" >“scaling mode”</td>
<td valign="top" >ENUM</td>
<td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td>
@@ -2819,6 +2819,61 @@ void intel_crt_init(struct drm_device *dev)
<td valign="top" >TBD</td>
</tr>
<tr>
<td valign="top" >“DEGAMMA_LUT”</td>
<td valign="top" >BLOB</td>
<td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to set the degamma lookup table
(LUT) mapping pixel data from the framebuffer before it is
given to the transformation matrix. The data is an interpreted
as an array of struct drm_color_lut elements. Hardware might
choose not to use the full precision of the LUT elements nor
use all the elements of the LUT (for example the hardware
might choose to interpolate between LUT[0] and LUT[4]). </td>
</tr>
<tr>
<td valign="top" >“DEGAMMA_LUT_SIZE”</td>
<td valign="top" >RANGE | IMMUTABLE</td>
<td valign="top" >Min=0, Max=UINT_MAX</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to gives the size of the lookup
table to be set on the DEGAMMA_LUT property (the size depends
on the underlying hardware).</td>
</tr>
<tr>
<td valign="top" >“CTM”</td>
<td valign="top" >BLOB</td>
<td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to set the current
transformation matrix (CTM) apply to pixel data after the
lookup through the degamma LUT and before the lookup through
the gamma LUT. The data is an interpreted as a struct
drm_color_ctm.</td>
</tr>
<tr>
<td valign="top" >“GAMMA_LUT”</td>
<td valign="top" >BLOB</td>
<td valign="top" >0</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to set the gamma lookup table
(LUT) mapping pixel data after to the transformation matrix to
data sent to the connector. The data is an interpreted as an
array of struct drm_color_lut elements. Hardware might choose
not to use the full precision of the LUT elements nor use all
the elements of the LUT (for example the hardware might choose
to interpolate between LUT[0] and LUT[4]).</td>
</tr>
<tr>
<td valign="top" >“GAMMA_LUT_SIZE”</td>
<td valign="top" >RANGE | IMMUTABLE</td>
<td valign="top" >Min=0, Max=UINT_MAX</td>
<td valign="top" >CRTC</td>
<td valign="top" >DRM property to gives the size of the lookup
table to be set on the GAMMA_LUT property (the size depends on
the underlying hardware).</td>
</tr>
<tr>
<td rowspan="20" valign="top" >i915</td>
<td rowspan="2" valign="top" >Generic</td>
<td valign="top" >"Broadcast RGB"</td>

62
Documentation/arm64/tagged-pointers.txt
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@@ -11,24 +11,56 @@ in AArch64 Linux.
The kernel configures the translation tables so that translations made
via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of
the virtual address ignored by the translation hardware. This frees up
this byte for application use, with the following caveats:
this byte for application use.
(1) The kernel requires that all user addresses passed to EL1
are tagged with tag 0x00. This means that any syscall
parameters containing user virtual addresses *must* have
their top byte cleared before trapping to the kernel.
(2) Non-zero tags are not preserved when delivering signals.
This means that signal handlers in applications making use
of tags cannot rely on the tag information for user virtual
addresses being maintained for fields inside siginfo_t.
One exception to this rule is for signals raised in response
to watchpoint debug exceptions, where the tag information
will be preserved.
Passing tagged addresses to the kernel
--------------------------------------
(3) Special care should be taken when using tagged pointers,
since it is likely that C compilers will not hazard two
virtual addresses differing only in the upper byte.
All interpretation of userspace memory addresses by the kernel assumes
an address tag of 0x00.
This includes, but is not limited to, addresses found in:
- pointer arguments to system calls, including pointers in structures
passed to system calls,
- the stack pointer (sp), e.g. when interpreting it to deliver a
signal,
- the frame pointer (x29) and frame records, e.g. when interpreting
them to generate a backtrace or call graph.
Using non-zero address tags in any of these locations may result in an
error code being returned, a (fatal) signal being raised, or other modes
of failure.
For these reasons, passing non-zero address tags to the kernel via
system calls is forbidden, and using a non-zero address tag for sp is
strongly discouraged.
Programs maintaining a frame pointer and frame records that use non-zero
address tags may suffer impaired or inaccurate debug and profiling
visibility.
Preserving tags
---------------
Non-zero tags are not preserved when delivering signals. This means that
signal handlers in applications making use of tags cannot rely on the
tag information for user virtual addresses being maintained for fields
inside siginfo_t. One exception to this rule is for signals raised in
response to watchpoint debug exceptions, where the tag information will
be preserved.
The architecture prevents the use of a tagged PC, so the upper byte will
be set to a sign-extension of bit 55 on exception return.
Other considerations
--------------------
Special care should be taken when using tagged pointers, since it is
likely that C compilers will not hazard two virtual addresses differing
only in the upper byte.

31
Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt Normal file
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@@ -0,0 +1,31 @@
OP-TEE Device Tree Bindings
OP-TEE is a piece of software using hardware features to provide a Trusted
Execution Environment. The security can be provided with ARM TrustZone, but
also by virtualization or a separate chip.
We're using "linaro" as the first part of the compatible property for
the reference implementation maintained by Linaro.
* OP-TEE based on ARM TrustZone required properties:
- compatible : should contain "linaro,optee-tz"
- method : The method of calling the OP-TEE Trusted OS. Permitted
values are:
"smc" : SMC #0, with the register assignments specified
in drivers/tee/optee/optee_smc.h
"hvc" : HVC #0, with the register assignments specified
in drivers/tee/optee/optee_smc.h
Example:
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};

2
Documentation/devicetree/bindings/arm/mali-utgard.txt
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2014, 2016 ARM Limited. All rights reserved.
* Copyright (C) 2014, 2016-2017 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.

7
Documentation/devicetree/bindings/arm/rockchip.txt
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@@ -77,6 +77,10 @@ Rockchip platforms device tree bindings
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
- Rockchip PX5 Evaluation board:
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
- Rockchip RK3368 evb:
Required root node properties:
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
@@ -92,6 +96,9 @@ Rockchip platforms device tree bindings
- Rockchip RK3229 Evaluation board:
- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
- Rockchip RK3229 Echo board:
- compatible = "rockchip,rk3229-echo", "rockchip,rk3229";
- Rockchip RK3288 Fennec board:
Required root node properties:
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";

45
Documentation/devicetree/bindings/chosen.txt
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@@ -52,3 +52,48 @@ This property is set (currently only on PowerPC, and only needed on
book3e) by some versions of kexec-tools to tell the new kernel that it
is being booted by kexec, as the booting environment may differ (e.g.
a different secondary CPU release mechanism)
linux,usable-memory-range
-------------------------
This property (arm64 only) holds a base address and size, describing a
limited region in which memory may be considered available for use by
the kernel. Memory outside of this range is not available for use.
This property describes a limitation: memory within this range is only
valid when also described through another mechanism that the kernel
would otherwise use to determine available memory (e.g. memory nodes
or the EFI memory map). Valid memory may be sparse within the range.
e.g.
/ {
chosen {
linux,usable-memory-range = <0x9 0xf0000000 0x0 0x10000000>;
};
};
The main usage is for crash dump kernel to identify its own usable
memory and exclude, at its boot time, any other memory areas that are
part of the panicked kernel's memory.
While this property does not represent a real hardware, the address
and the size are expressed in #address-cells and #size-cells,
respectively, of the root node.
linux,elfcorehdr
----------------
This property (currently used only on arm64) holds the memory range,
the address and the size, of the elf core header which mainly describes
the panicked kernel's memory layout as PT_LOAD segments of elf format.
e.g.
/ {
chosen {
linux,elfcorehdr = <0x9 0xfffff000 0x0 0x800>;
};
};
While this property does not represent a real hardware, the address
and the size are expressed in #address-cells and #size-cells,
respectively, of the root node.

58
Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt Normal file
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@@ -0,0 +1,58 @@
* Rockchip RK3126/RK3128 Clock and Reset Unit
The RK3126/RK3128 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
"rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
"rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "ext_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
Example: Clock controller node:
cru: cru@20000000 {
compatible = "rockchip,rk3128-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart2: serial@20068000 {
compatible = "rockchip,serial";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "sclk_uart", "pclk_uart";
};

2
Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -18,6 +18,7 @@ Required properties:
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
"allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
@@ -43,6 +44,7 @@ Required properties:
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80

63
Documentation/devicetree/bindings/cpufreq/cpufreq-rockchip.txt
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@@ -1,26 +1,57 @@
Binding for Rockchip's CPUFreq driver
===============================
Rockchip's CPUFreq driver attempts to read SoC version and leakage values
from eFuse, then supplies the OPP framework with 'prop' and 'supported
hardware' information respectively. This is based on operating-points-v2,
but the driver can also create the "cpufreq-dt" platform_device to
compatibility with operating-points.
Rockchip's CPUFreq driver attempts to read leakage value from eFuse
and get frequency count from pvtm, then supplies the OPP framework
with 'prop' information which is used to determine opp-microvolt-<name>
property of OPPS when it is parsed by the OPP framework. This is based
on operating-points-v2, but the driver can also create the "cpufreq-dt"
platform_device to compatibility with operating-points.
For more information about the expected DT format [See: ../opp/opp.txt].
Optional properties:
In 'operating-points-v2' table:
- leakage-voltage-sel: The property is an array of 3-tuples items, and
each item consists of leakage and voltage selector like
<min-leakage max-leakage volt-selector>.
min-leakage: minimum leakage in mA, ranges from 1 to 254
max-leakage: maximum leakage in mA, ranges from 1 to 254
voltage-selector: a sequence number which is used to math
opp-microvolt-L<number> roperty in OPP node
- nvmem-cells: A phandle to the soc_version and cpu_leakage data provided
by a nvmem device.
- nvmem-cell-names: Should be "soc_version" and "cpu_leakage"
- rockchip,leakage-voltage-sel: The property is an array of 3-tuples items, and
each item consists of leakage and voltage selector like
<min-leakage max-leakage volt-selector>.
min-leakage: minimum leakage in mA, ranges from 1 to 254.
max-leakage: maximum leakage in mA, ranges from 1 to 254.
voltage-selector: a sequence number which is used to math
opp-microvolt-L<number> roperty in OPP node.
- rockchip,pvtm-voltage-sel: The property is an array of 3-tuples items, and
each item consists of pvtm and voltage selector like
<min-pvtm max-pvtm volt-selector>.
min-pvtm: minimum frequency count in KHz.
max-pvtm: maximum frequency count in KHz.
voltage-selector: a sequence number which is used to math
opp-microvolt-L<number> roperty in OPP node.
- rockchip,pvtm-freq: Clock frequency in KHz, which is used to set the cpu clock
frequency before get frequency count of pvtm.
- rockchip,pvtm-volt: Voltage in uV, which is used to set the cpu voltage before
get frequency count of pvtm.
- rockchip,pvtm-ch: An array of two integers containing pvtm channel and clock
oscillation ring.
- rockchip,pvtm-sample-time: The number of milliseconds to wait for pvtm to
finish counting.
- rockchip,pvtm-number: An integer indicating the number of sampling points.
- rockchip,pvtm-error: An integer indicating the error between the sample
results.
- rockchip,pvtm-ref-temp: The SoC internal temperature in degree centigrade, the
min-pvtm and max-pvtm in 'leakage-voltage-sel' are
measured at reference temperature.
- rockchip,pvtm-temp-prop: An array of two integers containing proportional
constants which is used to convert the value at current
temperature to reference temperature. The first one is
used when current temperature is below reference
temperature. Conversely, The second one is used when
current temperature is above reference temperature.
- rockchip,pvtm-thermal-zone: A thermal zone node containing thermal sensor,
it's used to get the current temperature.
- nvmem-cells: A phandle to cpu_leakage data provided by a nvmem device.
- nvmem-cell-names: Should be "cpu_leakage"
Examples:
@@ -33,7 +64,7 @@ cpus {
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
leakage-voltage-sel = <
rockchip,leakage-voltage-sel = <
1 24 0
25 254 1
>;

2
Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
View File

@@ -3,6 +3,8 @@
Required properties:
- compatible: Should be one of the following.
- "rockchip,rk3128-dfi" - for RK3128 SoCs.
- "rockchip,rk3288-dfi" - for RK3288 SoCs.
- "rockchip,rk3368-dfi" - for RK3368 SoCs.
- "rockchip,rk3399-dfi" - for RK3399 SoCs.

9
Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt
View File

@@ -2,6 +2,9 @@
Required properties:
- compatible: Should be one of the following.
- "rockchip,rk3128-dmc" - for RK3128 SoCs.
- "rockchip,rk3288-dmc" - for RK3288 SoCs.
- "rockchip,rk3368-dmc" - for RK3368 SoCs.
- "rockchip,rk3399-dmc" - for RK3399 SoCs.
- devfreq-events: Node to get DDR loading, Refer to
Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt
@@ -19,6 +22,12 @@ Optional properties:
- ddr_timing: DDR timing need to pass to arm trust firmware
- upthreshold: The upthreshold to simpleondeamnd policy
- downdifferential: The downdifferential to simpleondeamnd policy
- vop-bw-dmc-freq: The property is an array of 3-tuples items, and
each item consists of bandwidth and frequency like
<min-bandwidth max-bandwidth frequency>.
min-bandwidth: minimum ddr bandwidth in Mbyte/sec.
max-bandwidth: maximum ddr bandwidth in Mbyte/sec.
frequency: ddr frequency in KHz.
Example:

3
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
View File

@@ -5,7 +5,9 @@ Required properties:
* "snps,dw-hdmi-tx"
* "fsl,imx6q-hdmi"
* "fsl,imx6dl-hdmi"
* "rockchip,rk3228-dw-hdmi"
* "rockchip,rk3288-dw-hdmi"
* "rockchip,rk3328-dw-hdmi"
* "rockchip,rk3399-dw-hdmi"
- reg: Physical base address and length of the controller's registers.
- interrupts: The HDMI interrupt number
@@ -22,6 +24,7 @@ Optional properties
- reg-io-width: the width of the reg:1,4, default set to 1 if not present
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
- hdcp1x-enable: enable hdcp1.x, enable if defined, disable if not defined
Example:
hdmi: hdmi@0120000 {

44
Documentation/devicetree/bindings/display/bridge/rk1000.txt Normal file
View File

@@ -0,0 +1,44 @@
Rockchip RK1000 TVEncoder
-------------------------------
The RK1000-TVE are RK1000 TV Encoder register block.
The chip is connected to an i2c bus.
Required properties:
- compatible: should be "rockchip,rk1000-tve"
- reg: I2C slave address
- rockchip,data-width: should be <18> or <24>
- rockchip,output: This describes the output face
- rockchip,ctl: phandle to the rk1000 core controller
Required node:
The rk1000 tve has one video port. its connection is modeled using the OF
graph binding specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 for LVDS input
Example
-------
rk1000-tve@42 {
status = "okay";
compatible = "rockchip,rk1000-tve";
reg = <0x42>;
rockchip,data-width = <24>;
rockchip,output = "rgb";
rockchip,ctl = <&rk1000_ctl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tve_in: port@0 {
reg = <0>;
tve_in_lvds: endpoint {
remote-endpoint = <&lvds_out_tve>;
};
};
};
};

9
Documentation/devicetree/bindings/display/panel/boe,mv238qum-n20.txt Normal file
View File

@@ -0,0 +1,9 @@
Boe Corporation 23.8" UHD TFT LCD panel
It has been designed to apply eDP(HBR2, 5.4Gbps) interface.
Required properties:
- compatible: should be "boe,mv238qum-n20"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

9
Documentation/devicetree/bindings/display/panel/lg,lm238wr2-spa1.txt Normal file
View File

@@ -0,0 +1,9 @@
LG Corporation 23.8" UHD TFT LCD panel
It has been designed to apply eDP(HBR2, 5.4Gbps) interface.
Required properties:
- compatible: should be "lg,lm238wr2-spa1"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

9
Documentation/devicetree/bindings/display/panel/lg,lm270wr3-ssa1.txt Normal file
View File

@@ -0,0 +1,9 @@
LG Corporation 27" UHD TFT LCD panel
It has been designed to apply eDP(HBR2, 5.4Gbps) interface.
Required properties:
- compatible: should be "lg,lm270wr3-ssa1"
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

49
Documentation/devicetree/bindings/display/panel/simple-panel.txt
View File

@@ -10,7 +10,15 @@ Optional properties:
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- enable-gpios: GPIO pin to enable or disable the panel
- reset-gpios: GPIO pin to reset the panel
- backlight: phandle of the backlight device attached to the panel
- reset-delay-ms: reset pulse width
- enable-delay-ms: takes for the panel to display
- prepare-delay-ms: take for the panel to receive video data
- disable-delay-ms: takes for the panel to power off
- unprepare-delay-ms: take for the panel to display off
- width-mm: physical panel width [mm]
- height-mm: physical panel height [mm]
Required properties when compatible is "simple-panel" or "simple-panel-dsi":
- display-timings: see display-timing.txt for information
@@ -19,8 +27,7 @@ Optional properties when compatible is a dsi devices:
- dsi,flags: dsi operation mode related flags
- dsi,format: pixel format for video mode
- dsi,lanes: number of active data lanes
- reset-gpios: GPIO pin to reset the panel
- reset-delay-ms: reset pulse width
- init-delay-ms: take for send command to panel
- panel-init-sequence: A byte stream formed by simple multiple dcs packets.
byte 0: dcs data type
byte 1: wait number of specified ms after dcs command transmitted
@@ -32,6 +39,11 @@ Optional properties when compatible is a dsi devices:
byte 2: packet payload length
byte 3 and beyond: number byte of payload
Optional for some special hardwre:
- power-invert:
if power-invert exist the panel power need to disable ldo when power on
and enable ldo when power off otherwise it's opposite.
Example:
panel: panel {
@@ -45,21 +57,26 @@ Example:
};
Or:
panel: panel {
&dsi {
panel@0 {
compatible = "simple-panel-dsi";
ddc-i2c-bus = <&panelddc>;
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio 90 0>;
reset-gpios = <&gpio 91 0>;
reset-delay-ms = <20>;
reg = <0>;
backlight = <&backlight>;
dsi,flags = <MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_VIDEO_SYNC_PULSE>;
power-supply = <&vcc_lcd>;
enable-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
reset-delay-ms = <120>;
init-delay-ms = <120>;
enable-delay-ms = <120>;
prepare-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
dsi,flags = <MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
@@ -68,7 +85,7 @@ Or:
d7 23 80 c0 d2 58
...
05 78 01 11
05 00 01 29
05 78 01 29
];
panel-exit-sequence = [
@@ -78,6 +95,7 @@ Or:
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <160000000>;
hactive = <1200>;
@@ -95,3 +113,4 @@ Or:
};
};
};
};

4
Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
View File

@@ -29,6 +29,10 @@ Required properties:
Port 0: contained 2 endpoints, connecting to the output of vop.
Port 1: contained 1 endpoint, connecting to the input of panel.
Optional properties
- vcc-supply: Regulator for eDP_AVDD_1V0.
- vccio-supply: Regulator for eDP_AVDD_1V8.
For the below properties, please refer to Analogix DP binding document:
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
- phys (required)

10
Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
View File

@@ -2,7 +2,11 @@ Rockchip specific extensions to the Synopsys Designware HDMI
================================
Required properties:
- compatible: "rockchip,rk3288-dw-hdmi",
- compatible: "rockchip,rk3228-dw-hdmi",
"rockchip,rk3288-dw-hdmi",
"rockchip,rk3328-dw-hdmi",
"rockchip,rk3366-dw-hdmi",
"rockchip,rk3368-dw-hdmi",
"rockchip,rk3399-dw-hdmi";
- reg: Physical base address and length of the controller's registers.
- clocks: phandle to hdmi iahb and isfr clocks.
@@ -20,7 +24,11 @@ Optional properties
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec",
phandle to the VPLL clock, name should be "vpll",
phandle to the GRF clock, name should be "grf".
phandle to the HDMI-PHY dclk, name should be "dclk".
- rockchip,phy-table: the parameter table of hdmi phy configuration.
- phys: phandle to third party HDMI PHY node
- phy-names: the string "hdmi_phy" when is found in a node, along with "phys"
attribute, provides phandle to HDMI PHY node
Example:
hdmi: hdmi@ff980000 {

117
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
View File

@@ -2,27 +2,33 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI
================================
Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
or "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- compatible: must be one of:
"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's APB clock(pclk) as
described in [1].
- resets : phandle to the reset of MIPI DSI APB Clock.
- reset-names : should be "apb".
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
Optional properties
- clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
"phy_cfg".phandle to the mipi dsi phy reference clock, name should be 'ref'.
- phys: phandle to third party MIPI PHY node
- clocks, clock-names:
phandle to the SNPS-PHY config clock, name should be "phy_cfg".
phandle to the SNPS-PHY PLL reference clock, name should be "ref".
phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
- phys: phandle to Non-SNPS PHY node
- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
attribute, provides phandle to MIPI PHY node
- resets : phandle to the reset of MIPI DSI APB Clock.
- reset-names : should be "apb".
- rockchip,dual-channel: for dual-channel panel, if not, don't configure
- rockchip,lane-rate: manually configure lane-rate, not necessary.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
@@ -32,16 +38,19 @@ Example:
For Rockchip RK3288:
mipi_dsi: mipi@ff960000 {
dsi0: dsi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
rockchip,grf = <&grf>;
rockchip,dual-channel = <&dsi1>;
rockchip,lane-rate = <900>;
status = "okay";
ports {
@@ -49,16 +58,17 @@ For Rockchip RK3288:
#size-cells = <0>;
reg = <1>;
mipi_in: port {
dsi0_in: port {
#address-cells = <1>;
#size-cells = <0>;
mipi_in_vopb: endpoint@0 {
dsi0_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
remote-endpoint = <&vopb_out_dsi0>;
};
mipi_in_vopl: endpoint@1 {
dsi0_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
remote-endpoint = <&vopl_out_dsi0>;
};
};
};
@@ -75,36 +85,55 @@ For Rockchip RK3288:
};
};
For Rockchip RK3368:
mipi_dsi_host: mipi-dsi-host@ff960000 {
compatible = "rockchip,rk3368-mipi-dsi";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
...
ports@1 {
dsi1: dsi@ff964000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff964000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI1>;
clock-names = "ref", "pclk";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "okay";
mipi_in: port {
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
mipi_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_mipi>;
dsi1_in: port {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi1>;
};
dsi1_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi1>;
};
};
};
};
dsi_panel: panel@0 {
compatible = "simple-panel-dsi";
reg = <0>;
dsi,lanes = <4>;
For Rockchip RK3368:
dsi: dsi@ff960000 {
compatible = "rockchip,rk3368-mipi-dsi";
clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
clock-names = "pclk", "hs_clk";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
...
ports {
port {
dsi_in_vop: endpoint {
remote-endpoint = <&vop_out_dsi>;
};
};
};
};
};

29
Documentation/devicetree/bindings/display/rockchip/rockchip-backlight.txt Normal file
View File

@@ -0,0 +1,29 @@
Rockchip DRM backlight device
================================
Rockchip display controller(see VOP bindings[0]) support CABC function,
and the CABC function required using VOP self pwm to control backlight,
This backlight device manager the backlight PWM, auto select correct
PWM for backlight.
Required properties:
- compatible: Should be "rockchip,drm-backlight"
Other properties are same to commom PWM backlight bindings[1].
[0]: Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
[1]: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
example:
backlight {
compatible = "rockchip,drm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
};

14
Documentation/devicetree/bindings/display/rockchip/rockchip-drm.txt
View File

@@ -11,9 +11,23 @@ Required properties:
of vop devices. vop definitions as defined in
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
Optional properties
- backlight: spacial backlight required by cabc function.
- secure-memory-region: phandle to a node describing secure memory
- clocks: include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: optional include
hdmi-tmds-pll: special pll required by some hdmi-vop design,
if there is no hdmi plug, also can reuse for
common display pll.
default-vop-pll: common display pll.
example:
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopl_out>, <&vopb_out>;
backlight = <&backlight>
clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
clock-names = "hdmi-tmds-pll", "default-vop-pll";
};

71
Documentation/devicetree/bindings/video/rockchip-lvds.txt → Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
View File

@@ -2,10 +2,18 @@ Rockchip RK3288 LVDS interface
================================
Required properties:
- compatible: "rockchip,rk3288-lvds";
- compatible: matching the soc type, one of
- "rockchip,rk3126-lvds";
- "rockchip,rk3288-lvds";
- "rockchip,rk3366-lvds";
- "rockchip,rk3368-lvds";
- reg: physical base address of the controller and length
of memory mapped region.
- reg-names: the name to indicate register. example:
- "mipi_lvds_phy": lvds phy register, this's included in the MIPI phy module
- "mipi_lvds_ctl": lvds control register, this's included in the MIPI
controller module
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: must contain "pclk_lvds"
@@ -16,12 +24,9 @@ Required properties:
- rockchip,grf: phandle to the general register files syscon
- rockchip,data-mapping: should be "vesa" or "jeida",
This describes how the color bits are laid out in the
serialized LVDS signal.
- rockchip,data-width : should be <18> or <24>;
- rockchip,output: should be "rgb", "lvds" or "duallvds",
This describes the output face.
Optional properties
- pinctrl-names: must contain a "lcdc" entry.
- pinctrl-0: pin control group to be used for this controller.
Required nodes:
@@ -33,13 +38,45 @@ Their connections are modeled using the OF graph bindings specified in
- video port 0 for the VOP inputs
- video port 1 for either a panel or subsequent encoder
the lvds panel described by
Documentation/devicetree/bindings/display/panel/simple-panel.txt
- rockchip,data-mapping: should be "vesa" or "jeida",
This describes how the color bits are laid out in the
serialized LVDS signal.
- rockchip,data-width : should be <18> or <24>;
- rockchip,output: should be "rgb", "lvds" or "duallvds",
This describes the output face.
- ports for remote LVDS output
Example:
lvds_panel: lvds-panel {
status = "okay";
compatible = "simple-panel";
enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
rockchip,data-mapping = "jeida";
rockchip,data-width = <24>;
rockchip,output = "rgb";
ports {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
For Rockchip RK3288:
lvds: lvds@ff96c000 {
compatible = "rockchip,rk3288-lvds";
rockchip,grf = <&grf>;
reg = <0xff96c000 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_ctl>;
avdd1v0-supply = <&vdd10_lcd>;
avdd1v8-supply = <&vcc18_lcd>;
avdd3v3-supply = <&vcca_33>;
@@ -72,3 +109,23 @@ Example:
};
};
};
For Rockchip RK3368:
lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
power-domains = <&power RK3368_PD_VIO>;
rockchip,grf = <&grf>;
pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_lcdc>;
ports {
...
};
};

16
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
View File

@@ -7,14 +7,26 @@ buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3126-vop";
"rockchip,rk3288-vop";
"rockchip,rk3368-vop";
"rockchip,rk3366-vop";
"rockchip,rk3366-vop-lit";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
"rockchip,rk322x-vop";
"rockchip,rk3328-vop";
- reg: Address and length of the register set for the device.
- reg-names: The names of register regions. contain following regions:
- "regs" : (Required) Base address and size of the controllers.
- "cabc_lut" : (Optinal) cabc function lut table registers,
take care of this register's length, driver would use
register's length to decide cabc lut table size.
- "gamma_lut" : (Optinal) gamma function lut table registers,
take care of this register's length, driver would use
register's length to decide gamma table size.
- interrupts: should contain a list of all VOP IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
@@ -26,6 +38,7 @@ Required properties:
aclk_vop: for ddr buffer transfer.
hclk_vop: for ahb bus to R/W the phy regs.
dclk_vop: pixel clock.
dclk_source: optinal, dclk sources from display plls.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
@@ -43,7 +56,8 @@ Example:
SoC specific DT entry:
vopb: vopb@ff930000 {
compatible = "rockchip,rk3288-vop";
reg = <0xff930000 0x19c>;
reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

43
Documentation/devicetree/bindings/display/rockchip/rockchip_drm_tve.txt Normal file
View File

@@ -0,0 +1,43 @@
Rockchip specific extensions to the TVE
================================
Required properties:
- compatible: "rockchip,rk3328-tve";
- reg: Physical base address and length of the controller's registers.
- ports: contain a port node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt
- rockchip,saturation: the value for TVE_COLOR_BUSRT_SAT(0x78)
- rockchip,brightcontrast: the value for TVE_BRIGHTNESS_CONTRAST(0x90)
- rockchip,adjtiming: the value for TVE_HOR_TIMING3(0x0c)
- rockchip,lumafilter0: the value for TVE_LUMA_FILTER1(0x14)
- rockchip,lumafilter1: the value for TVE_LUMA_FILTER2(0x18)
- rockchip,lumafilter2: the value for TVE_LUMA_FILTER3(0x1c)
- rockchip,daclevel: the value is used to adjust the voltage amplitude of the CVBS
- rockchip,dac1level: only for rv1108 rk322x and rk3328
Example:
tve: tve@ff373e00 {
compatible = "rockchip,rk3328-tve";
reg = <0x0 0xff373e00 0x0 0x100>,
<0x0 0xff420000 0x0 0x10000>;
rockchip,saturation = <0x00376749>;
rockchip,brightcontrast = <0x0000a305>;
rockchip,adjtiming = <0xb6c00880>;
rockchip,lumafilter0 = <0x01ff0000>;
rockchip,lumafilter1 = <0xf40200fe>;
rockchip,lumafilter2 = <0xf332d70c>;
rockchip,daclevel = <0x22>;
rockchip,dac1level = <0x7>;
status = "disabled";
ports {
tve_in: port {
#address-cells = <1>;
#size-cells = <0>;
tve_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_tve>;
};
};
};
};

130
Documentation/devicetree/bindings/dram/rk3399_dram_timing.txt Normal file
View File

@@ -0,0 +1,130 @@
* rk3399 dram default timing is at arch/arm64/boot/dts/rk3399_dram_default_timing.dtsi
Required properties:
- compatible : Should be "rockchip,ddr-timing"
- ddr3_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h.
It select DDR3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected
according to "Speed Bin" in DDR3 datasheet, DO NOT use smaller "Speed Bin" than
DDR3 exactly is.
- pd_idle : Defines the power-down mode auto entry controller clocks.
This parameter defines the number of idle controller clocks that can elapse
before the controller will automatically issue an entry into the appropriate
power-down low power state.
- sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating
auto entry periodic cycles.
This parameter defines the number of long count sequences that can elapse
before the controller will automatically issue an entry into the Self-Refresh
or Self-Refresh with Memory Clock Gating low power state.
- sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating
auto entry periodic cycles.
This parameter defines the number of long count sequences that can elapse before
the controller will automatically issue an entry into the Self-Refresh with
Memory and Controller Clock Gating low power state.
- srpd_lite_idle : Define the Lite Self-Refresh Power-Down auto entry periodic
cycles.
This parameter defines the number of long count sequences that can elapse
before the controller will automatically issue an entry into the
Lite Self-Refresh Power-Down low power state.
- standby_idle : Define the standby mode auto entry periodic cycles.
- auto_lp_dis_freq : It's defined the auto low down mode frequency in MHz (Mega Hz),
when ddr freq greater than or equal this setting value, auto power-down will disable.
- ddr3_dll_dis_freq : It's defined the DDR3 dll bypass frequency in MHz (Mega Hz),
when ddr freq less than or equal this setting value, DDR3 dll will bypssed.
note: if dll was bypassed, the odt also stop working.
- phy_dll_dis_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz),
when ddr freq less than or equal this setting value, phy dll will bypssed.
note: phy dll and phy odt are independent.
- ddr3_odt_dis_freq : Defined the DDR3 odt disable frequency in
MHz (Mega Hz), when ddr frequency less then or equal ethis setting value, the DDR3
ODT are disabled.
- ddr3_drv : Define the driver strength in ohm when connect DDR3.
- ddr3_odt : Define the ODT in ohm when connect DDR3.
- phy_ddr3_ca_drv : Define the PHY CA driver strength in ohm when connect DDR3.
- phy_ddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect DDR3.
- phy_ddr3_odt : Define the phy odt in ohm when connect DDR3.
- lpddr3_odt_dis_freq : Defined the LPDDR3 odt disable frequency in
MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR3
ODT are disabled.
- lpddr3_drv : Define the driver strength in ohm when connect LPDDR3.
- lpddr3_odt : Define the ODT in ohm when connect LPDDR3.
- phy_lpddr3_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR3.
- phy_lpddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR3.
- phy_lpddr3_odt : Define the phy odt in ohm when connect LPDDR3.
- lpddr4_odt_dis_freq : Defined the LPDDR4 odt disable frequency in
MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR4
ODT are disabled.
- lpddr4_drv : Define the driver strength in ohm when connect LPDDR4.
- lpddr4_dq_odt : Define the DQ ODT in ohm when connect LPDDR4.
- lpddr4_ca_odt : Define the CA ODT in ohm when connect LPDDR4.
- phy_lpddr4_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR4.
- phy_lpddr4_ck_cs_drv : Define the PHY CLK and CS driver strength in ohm when connect LPDDR4.
- phy_lpddr4_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR4.
- phy_lpddr4_odt : Define the phy odt in ohm when connect LPDDR4.
Example:
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <21>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
auto_lp_dis_freq = <666>;
ddr3_dll_dis_freq = <300>;
phy_dll_dis_freq = <260>;
ddr3_odt_dis_freq = <666>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_ddr3_odt = <PHY_DRV_ODT_240>;
lpddr3_odt_dis_freq = <666>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>;
phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>;
phy_lpddr3_odt = <PHY_DRV_ODT_240>;
lpddr4_odt_dis_freq = <933>;
lpddr4_drv = <LP4_PDDS_60ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_odt = <PHY_DRV_ODT_60>;
};
};

39
Documentation/devicetree/bindings/leds/leds-pca9532.txt Normal file
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@@ -0,0 +1,39 @@
*NXP - pca9532 PWM LED Driver
The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
The PWM support 256 steps.
Required properties:
- compatible:
"nxp,pca9530"
"nxp,pca9531"
"nxp,pca9532"
"nxp,pca9533"
- reg - I2C slave address
Each led is represented as a sub-node of the nxp,pca9530.
Optional sub-node properties:
- label: see Documentation/devicetree/bindings/leds/common.txt
- type: Output configuration, see dt-bindings/leds/leds-pca9532.h (default NONE)
- linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt
Example:
#include <dt-bindings/leds/leds-pca9532.h>
leds: pca9530@60 {
compatible = "nxp,pca9530";
reg = <0x60>;
red-power {
label = "pca:red:power";
type = <PCA9532_TYPE_LED>;
};
green-power {
label = "pca:green:power";
type = <PCA9532_TYPE_LED>;
};
};
For more product information please see the link below:
http://nxp.com/documents/data_sheet/PCA9532.pdf

13
Documentation/devicetree/bindings/display/rockchip/rockchip-rga.txt → Documentation/devicetree/bindings/media/rockchip-rga.txt
View File

@@ -1,36 +1,33 @@
device-tree bindings for rockchip 2D raster graphic acceleration controller (RGA)
RGA is a separate 2D raster graphic acceleration unit. It accelerates 2D
RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
graphics operations, such as point/line drawing, image scaling, rotation,
BitBLT, alpha blending and image blur/sharpness.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3228-rga";
"rockchip,rk3288-rga";
"rockchip,rk3399-rga";
- interrupts: RGA interrupt number.
- interrupts: RGA interrupt specifier.
- clocks: phandle to RGA sclk/hclk/aclk clocks
- clock-names: should be "aclk" "hclk" and "sclk"
- clock-names: should be "aclk", "hclk" and "sclk"
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: should be "core" "axi" and "ahb"
- reset-names: should be "core", "axi" and "ahb"
Example:
SoC specific DT entry:
SoC-specific DT entry:
rga: rga@ff680000 {
compatible = "rockchip,rk3399-rga";
reg = <0xff680000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rga";
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
clock-names = "aclk", "hclk", "sclk";
resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
reset-names = "core, "axi", "ahb";
status = "disabled";
};

24
Documentation/devicetree/bindings/mfd/rk1000-core.txt Normal file
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@@ -0,0 +1,24 @@
RK1000 Multi-functional device
The RK1000-CORE are RK1000 control register block.
The chip is connected to an i2c bus.
Required properties:
- compatible : "rockchip,rk1000-ctl"
- reg: I2C slave address
- reset-gpios : the reset pin
- clocks : phandle and clock specifier
- clock-names : "mclk"
Example:
rk1000-ctl@40 {
compatible = "rockchip,rk1000-ctl";
reg = <0x40>;
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
status = "okay";
};

217
Documentation/devicetree/bindings/mfd/rk816.txt Normal file
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@@ -0,0 +1,217 @@
RK816 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk816"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs).
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- gpio-controller: Specifies that the node is a gpio controller when you attempt to
use the TS pin of RK816 by GPIO general interface.
- #gpio-cells: Should be two. The first cell is the GPIO number and the second cell
is used to specify the GPIO polarity.
- wakeup-source: Flag to indicate this device can wake system (suspend/resume)
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
Regulators: All the regulators of RK816 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK816 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK816 datasheet.
- DCDC_REGn
- valid values for n are 1 to 4.
- LDO_REGn
- valid values for n are 1 to 6.
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Gpio, Rtc, Pwrkey: the node are represented like below. When you attempt to enable
the module, setting the "status" to be "okay", otherwise "disabled".
rtc {
status = "okay";
};
pwrkey {
status = "okay";
};
gpio {
status = "okay";
};
Example:
rk816: pmic@1a {
compatible = "rockchip,rk816";
status = "disabled";
reg = <0x1a>;
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
gpio-controller;
#gpio-cells = <2>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
rtc {
status = "okay";
};
pwrkey {
status = "okay";
};
gpio {
status = "okay";
};
regulators {
vdd_cpu: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc33_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_tp: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc18_lcd: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};

1
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
View File

@@ -13,6 +13,7 @@ Required Properties:
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
before RK3288
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322X
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399

22
Documentation/devicetree/bindings/net/ti,dp83867.txt
View File

@@ -2,13 +2,29 @@
Required properties:
- reg - The ID number for the phy, usually a small integer
- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values. Required only if interface type is
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
for applicable values. Required only if interface type is
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
for applicable values
Optional property:
- ti,min-output-impedance - MAC Interface Impedance control to set
the programmable output impedance to
minimum value (35 ohms).
- ti,max-output-impedance - MAC Interface Impedance control to set
the programmable output impedance to
maximum value (70 ohms).
- ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
for applicable values.
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
takes precedence.
Default child nodes are standard Ethernet PHY device
nodes as described in Documentation/devicetree/bindings/net/phy.txt

2
Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
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@@ -3,7 +3,9 @@
Required properties:
- compatible: Should be one of the following.
- "rockchip,rk3066a-efuse" - for RK3066a SoCs.
- "rockchip,rk3128-efuse" - for RK3128 SoCs.
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
- "rockchip,rk322x-efuse" - for RK322x SoCs.
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
- "rockchip,rk3288-secure-efuse" - for RK3288 SoCs.
- "rockchip,rk3328-efuse" - for RK3328 SoCs.

37
Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi-phy.txt Normal file
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@@ -0,0 +1,37 @@
ROCKCHIP HDMI PHY WITH INNO IP BLOCK
Required properties:
- compatible : "rockchip,rk3228-hdmi-phy",
"rockchip,rk3328-hdmi-phy";
- reg : the address offset of register for hdmi phy configuration.
- #phy-cells : must be 0. See ./phy-bindings.txt for details.
- clocks and clock-names:
- the "sysclk" clock is required by the phy module, used to system
control and register configuration
- the "refclk" clock is reference crystal oscillator clock input
to PLL
- #clock-cells: should be 0.
- clock-output-names : shall be the corresponding names of the outputs.
Example:
hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
#phy-cells = <0>;
clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>;
clock-names = "sysclk", "refclk";
#clock-cells = <0>;
clock-output-names = "hdmiphy_phy";
status = "disabled";
};
Then the PHY can be used in other nodes such as:
hdmi: hdmi@200a0000 {
compatible = "rockchip,rk3228-dw-hdmi";
...
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
...
};

43
Documentation/devicetree/bindings/phy/phy-rockchip-inno-mipi-dphy.txt
View File

@@ -1,7 +1,9 @@
ROCKCHIP MIPI DPHY WITH INNO IP BLOCK
Required properties:
- compatible : should be "rockchip,rk3368-mipi-dphy";
- compatible : must be one of:
"rockchip,rk3366-mipi-dphy";
"rockchip,rk3368-mipi-dphy";
- reg : the address offset of register for mipi-dphy configuration.
- #phy-cells : must be 0. See ./phy-bindings.txt for details.
- clocks and clock-names:
@@ -9,8 +11,9 @@ Required properties:
configuration
- the "ref" clock is used to get the rate of the reference clock
provided to the PHY module
- rockchip,dsi-panel : phandle to MIPI DSI panel node, used to get the display
timing of the panel provided to the PHY module.
- clock-output-names: from common clock binding.
See ../clocks/clock-bindings.txt for details.
- #clock-cells : from common clock binding; shall be set to 0.
Optional properties
- resets : phandle to the reset of MIPI DSI PHY APB clock.
@@ -20,25 +23,25 @@ Example:
For Rockchip RK3368
mipi_dphy: mipi-dphy@ff968000 {
compatible = "rockchip,rk3368-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
#phy-cells = <0>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
clock-names = "ref", "pclk";
resets = <&cru SRST_MIPIDPHYTX>;
reset-names = "apb";
rockchip,dsi-panel = <&dsi_panel>;
};
mipi_dphy: mipi-dphy@ff968000 {
compatible = "rockchip,rk3368-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
clock-names = "ref", "pclk";
clock-output-names = "mipi_dphy_pll";
#clock-cells = <0>;
resets = <&cru SRST_MIPIDPHYTX>;
reset-names = "apb";
#phy-cells = <0>;
};
Then the PHY can be used in other nodes such as:
mipi-dsi-host@ff960000 {
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
dsi_panel: panel {
dsi,lanes = 4;
dsi@ff960000 {
...
clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
clock-names = "pclk", "hs_clk";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
...
};
};

2
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
View File

@@ -2,6 +2,8 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
Required properties (phy (parent) node):
- compatible : should be one of the listed compatibles:
* "rockchip,rk3128-usb2phy"
* "rockchip,rk322x-usb2phy"
* "rockchip,rk3328-usb2phy"
* "rockchip,rk3366-usb2phy"
* "rockchip,rk3368-usb2phy"

18
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@@ -19,11 +19,19 @@ The pins are grouped into up to 5 individual pin banks which need to be
defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
"rockchip,rk3328-pinctrl", "rockchip,rk3366-pinctrl"
"rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl"
- compatible: should be
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
"rockchip,rk3128-pinctrl": for Rockchip RK3128
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288
"rockchip,rk3328-pinctrl": for Rockchip RK3328
"rockchip,rk3366-pinctrl": for Rockchip RK3366
"rockchip,rk3368-pinctrl": for Rockchip RK3368
"rockchip,rk3399-pinctrl": for Rockchip RK3399
- rockchip,grf: phandle referencing a syscon providing the
"general register files"

24
Documentation/devicetree/bindings/power/bq25703.txt Normal file
View File

@@ -0,0 +1,24 @@
Binding for TI bq25703 Li-Ion Charger
Required properties:
- compatible: Should contain one of the following:
* "ti,bq25703"
- reg: integer, i2c address of the device.
- ti,max-charge-voltage: integer, maximum charging voltage (in uV);
- ti,charge-current: integer, maximum charging current (in uA);
- ti,minimum-sys-voltage: integer, when battery is charging and it is below
minimum system voltage, the system will be regulated above
minimum-sys-voltage setting (in uV);
Optional properties:
Example:
bq25703@6b {
compatible = "ti,bq25703";
reg = <0x6b>;
ti,max-charge-voltage = <4200000>;
ti,charge-current = <1000000>;
ti,minimum-sys-voltage = <3600000>;
};

33
Documentation/devicetree/bindings/power/cw2015_battery.txt Normal file
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@@ -0,0 +1,33 @@
Binding for CW201X Battery
Required properties:
- compatible: Should contain one of the following:
* "cw201x"
- reg: integer, smbus address of the device.
- tvirtual_power: integer, test power, if battery is not exist;
- monitor_sec: integer, delay time of queue_delayed_work (s);
- bat_config_info: battery curve information;
- divider_res1: divider resistor of dual battery;
- divider_res2: divider resistor of dual battery;
Optional properties:
Example:
cw2015@62 {
status = "disabled";
compatible = "cw201x";
reg = <0x62>;
bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48
0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24
0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45
0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E
0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D
0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52
0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB
0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>;
monitor_sec = <5>;
virtual_power = <0>;
divider_res1 = <200>;
divider_res2 = <200>;
};

7
Documentation/devicetree/bindings/power/rockchip-io-domain.txt
View File

@@ -32,6 +32,7 @@ SoC is on the same page.
Required properties:
- compatible: should be one of:
- "rockchip,rk3188-io-voltage-domain" for rk3188
- "rockchip,rk322x-io-voltage-domain" for rk3228
- "rockchip,rk3288-io-voltage-domain" for rk3288
- "rockchip,rk3328-io-voltage-domain" for rk3328
- "rockchip,rk3366-io-voltage-domain" for rk3366
@@ -60,6 +61,12 @@ Possible supplies for rk3188:
- vccio1-supply: The supply connected to VCCIO1.
Sometimes also labeled VCCIO1 and VCCIO2.
Possible supplies for rk322x:
- vccio1-supply: The supply connected to VCCIO1.
- vccio2-supply: The supply connected to VCCIO2.
- vccio3-supply: The supply connected to VCCIO3.
- vccio4-supply: The supply connected to VCCIO4.
Possible supplies for rk3288:
- audio-supply: The supply connected to APIO4_VDD.
- bb-supply: The supply connected to APIO5_VDD.

14
Documentation/devicetree/bindings/power/sy6982c-charger.txt Normal file
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@@ -0,0 +1,14 @@
Binding for sy6982c Charger
Required properties:
- compatible: Should contain one of the following:
* "sy6982c-charger"
- extcon: extcon specifier for the Charger.
Example:
sy6982c {
status = "okay";
compatible = "sy6982c-charger";
extcon = <&u2phy0>;
};

4
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
View File

@@ -12,9 +12,9 @@ Required properties:
- For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
- There is one clock that's used both to derive the functional clock
for the device and as the bus clock.
- For newer hardware (rk3328): specified by name
- For newer hardware (rk3328 and future socs): specified by name
- "pwm": This is used to derive the functional clock.
- "pclk": This is the bus clock.
- "pclk": This is the APB bus clock.
- #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
for a description of the cell format.

28
Documentation/devicetree/bindings/soc/rockchip/rockchip-devinfo-reserved-memory.txt Normal file
View File

@@ -0,0 +1,28 @@
Rockchip devinfo reserved memory device tree bindings
=======================================================
Dev Info Device Node:
=======================
static allocation a specific range of reserved memory
Required properties:
-----------------
- compatible: Should be
"rockchip,stb-devinfo"
- reg: standard definition
Example:
-----
/* RK3399 */
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
...
stb_devinfo: stb-devinfo@00000000 {
compatible = "rockchip,stb-devinfo";
reg = <0x0 0x0 0x0 0x0>;
};
};

57
Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt
View File

@@ -1,7 +1,11 @@
* the suspend mode config
- compatible: "rockchip,pm-config"
Compatibility with rk3399
Required properties:
- compatible: Should be one of the following.
- "rockchip,pm-rk322x" - for RK322x SOCs.
- "rockchip,pm-rk3288" - for RK3288 SOCs.
- "rockchip,pm-rk3368" - for RK3368 SoCs.
- "rockchip,pm-rk3399" - for RK3399 SoCs.
- rockchip,sleep-mode-config : the sleep mode config,
ARMOFF, OSC disabled ...
@@ -12,6 +16,55 @@
- rockchip,pwm-regulator-config: the pwm regulator name.
Example:
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk322x";
status = "disabled";
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_GTCLKS
|RKPM_CTR_IDLESRAM_MD
)
>;
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk3288";
status = "disabled";
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_PWR_DMNS
|RKPM_CTR_GTCLKS
|RKPM_CTR_PLLS
|RKPM_CTR_ARMOFF_LPMD
)
>;
rockchip,wakeup-config = <
(0
| RKPM_GPIO_WKUP_EN
)
>;
rockchip,pwm-regulator-config = <
(0
| PWM2_REGULATOR_EN
)
>;
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk3368";
status = "disabled";
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMOFF_LOGPD
| RKPM_SLP_PMU_PLLS_PWRDN
| RKPM_SLP_PMU_PMUALIVE_32K
| RKPM_SLP_SFT_PLLS_DEEP
| RKPM_SLP_PMU_DIS_OSC
| RKPM_SLP_SFT_PD_NBSCUS
)
>;
};
rockchip_suspend: rockchip_suspend {
compatible = "rockchip,pm-rk3399";
status = "okay";

14
Documentation/devicetree/bindings/soc/rockchip/rockchip-pvtm.txt
View File

@@ -11,8 +11,13 @@ Required properties:
- "rockchip,rk3366-pmu-pvtm" - for RK3366 SoCs.
- "rockchip,rk3399-pvtm" - for RK3399 SoCs.
- "rockchip,rk3399-pmu-pvtm" - for RK3399 SoCs.
- clocks: list of the clock controller input clock identifiers.
- clock-names: list of the clock controller input clock names.
- clocks: Must contain an entry for each entry in clock-names.
See ../../clocks/clock-bindings.txt for details.
- clock-names: Should be "core_l", "core_b", "gpu", "ddr" and "pmu".
- resets: Must contain an entry for each entry in reset-names.
See ../../reset/reset.txt for details.
- reset-names: Should be "core_l", "core_b", "gpu", "ddr" and "pmu".
Example:
@@ -27,7 +32,10 @@ grf: syscon@ff770000 {
pvtm: pvtm {
compatible = "rockchip,rk3399-pvtm";
clocks = <&cru SCLK_PVTM_CORE_L>, <&cru SCLK_PVTM_CORE_B>,
<&cru SCLK_PVTM_GPU>, <&cru SCLK_PVTM_DDR>;
<&cru SCLK_PVTM_GPU>, <&cru SCLK_PVTM_DDR>;
clock-names = "core_l", "core_b", "gpu", "ddr";
resets = <&cru SRST_PVTM_CORE_L>, <&cru SRST_PVTM_CORE_B>,
<&cru SRST_PVTM_GPU>, <&cru SRST_PVTM_DDR>;
reset-names = "core_l", "core_b", "gpu", "ddr";
};
}

24
Documentation/devicetree/bindings/sound/rockchip,hdmi-analog.txt Normal file
View File

@@ -0,0 +1,24 @@
ROCKCHIP Built-in HDMI and external audio codec which use the same
I2S interface(such as RK3368)
Use simple-audio-card can be if only HDMI or codec ic
Required properties:
- compatible: "rockchip,rk3368-hdmi-analog"
- rockchip,cpu: The phandle of the Rockchip I2S controller that's
connected to the CODEC
- rockchip,codec: The phandle of audio codecs, should contain both
codec ic and HDMI
Example:
sound {
compatible = "rockchip,rk3368-hdmi-analog";
rockchip,cpu = <&i2s_8ch>;
rockchip,codec = <&es8316>, <&hdmi>;
rockchip,widgets = "Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
rockchip,routing = "Mic Jack", "micbias",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
};

20
Documentation/devicetree/bindings/sound/rockchip,rk1000-codec.txt Normal file
View File

@@ -0,0 +1,20 @@
* Rockchip RK1000 codec
Required properties:
- compatible: "rockchip,rk1000-codec"
- reg : the I2C address of the device.
- rockchip,spk-en-gpio: the enable gpio of spk.
- rockchip,pa-en-time-ms: pa enable dealy time(ms).
- rockchip,ctl: phandle to the rk1000 core controller.
Example for rk1000 codec:
rk1000_codec: rk1000-codec@60 {
compatible = "rockchip,rk1000_codec";
reg = <0x60>;
rockchip,spk-en-gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
rockchip,pa-en-time-ms = <5000>;
rockchip,ctl = <&rk1000_ctl>;
status = "okay";
};

1
Documentation/devicetree/bindings/sound/rockchip-spdif.txt
View File

@@ -9,6 +9,7 @@ Required properties:
- compatible: should be one of the following:
- "rockchip,rk3066-spdif"
- "rockchip,rk3188-spdif"
- "rockchip,rk3228-spdif"
- "rockchip,rk3288-spdif"
- "rockchip,rk3328-spdif"
- "rockchip,rk3366-spdif"

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@@ -128,6 +128,7 @@ lacie LaCie
lantiq Lantiq Semiconductor
lenovo Lenovo Group Ltd.
lg LG Corporation
linaro Linaro Limited
linux Linux-specific binding
lsi LSI Corp. (LSI Logic)
lltc Linear Technology Corporation

28
Documentation/devicetree/bindings/video/rockchip_enc.txt Normal file
View File

@@ -0,0 +1,28 @@
Device-Tree bindings for Rockchip Encoder.
Required properties:
- compatible: There are several encoder IP inside rockchip chips. The value
should be one of "rockchip,rkvenc", "rockchip,vepu", "rockchip,h265e"
Example:
DT entry:
vepu: vepu@ff340000 {
compatible = "rockchip,rk3328-vepu", "rockchip,vepu";
rockchip,grf = <&grf>;
iommu_enabled = <1>;
iommus = <&vepu_mmu>;
reg = <0x0 0xff340000 0x0 0x400>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_RKVENC_H264_H>,
<&cru SRST_RKVENC_H264_A>;
reset-names = "video_h", "video_a";
rockchip,srv = <&venc_srv>;
mode_bit = <11>;
mode_ctrl = <0x40c>;
name = "vepu";
allocator = <1>;
status = "disabled";
};

9
Documentation/devicetree/bindings/video/rockchip_mpp.txt Normal file
View File

@@ -0,0 +1,9 @@
Device-Tree bindings for Rockchip MPP Service.
Required properties:
- compatible: the value must be "rockchip,mpp_service"
Example:
venc_srv: venc_srv {
compatible = "rockchip,mpp_service";
};

21
Documentation/dma-buf-sharing.txt
View File

@@ -353,7 +353,26 @@ Being able to mmap an export dma-buf buffer object has 2 main use-cases:
handles, too). So it's beneficial to support this in a similar fashion on
dma-buf to have a good transition path for existing Android userspace.
No special interfaces, userspace simply calls mmap on the dma-buf fd.
No special interfaces, userspace simply calls mmap on the dma-buf fd, making
sure that the cache synchronization ioctl (DMA_BUF_IOCTL_SYNC) is *always*
used when the access happens. This is discussed next paragraphs.
Some systems might need some sort of cache coherency management e.g. when
CPU and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing dma-buf device drivers vfunc hooks. Userspace can make
use of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence
would be used like following:
- mmap dma-buf fd
- for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2. read/write
to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
want (with the new data being consumed by the GPU or say scanout device)
- munmap once you don't need the buffer any more
Therefore, for correctness and optimal performance, systems with the memory
cache shared by the GPU and CPU i.e. the "coherent" and also the
"incoherent" are always required to use SYNC_START and SYNC_END before and
after, respectively, when accessing the mapped address.
2. Supporting existing mmap interfaces in importers

1
Documentation/ioctl/ioctl-number.txt
View File

@@ -307,6 +307,7 @@ Code Seq#(hex) Include File Comments
0xA3 80-8F Port ACL in development:
<mailto:tlewis@mindspring.com>
0xA3 90-9F linux/dtlk.h
0xA4 00-1F uapi/linux/tee.h Generic TEE subsystem
0xAA 00-3F linux/uapi/linux/userfaultfd.h
0xAB 00-1F linux/nbd.h
0xAC 00-1F linux/raw.h

16
Documentation/kdump/kdump.txt
View File

@@ -18,7 +18,7 @@ memory image to a dump file on the local disk, or across the network to
a remote system.
Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64,
s390x and arm architectures.
s390x, arm and arm64 architectures.
When the system kernel boots, it reserves a small section of memory for
the dump-capture kernel. This ensures that ongoing Direct Memory Access
@@ -249,6 +249,13 @@ Dump-capture kernel config options (Arch Dependent, arm)
AUTO_ZRELADDR=y
Dump-capture kernel config options (Arch Dependent, arm64)
----------------------------------------------------------
- Please note that kvm of the dump-capture kernel will not be enabled
on non-VHE systems even if it is configured. This is because the CPU
will not be reset to EL2 on panic.
Extended crashkernel syntax
===========================
@@ -312,6 +319,8 @@ Boot into System Kernel
any space below the alignment point may be overwritten by the dump-capture kernel,
which means it is possible that the vmcore is not that precise as expected.
On arm64, use "crashkernel=Y[@X]". Note that the start address of
the kernel, X if explicitly specified, must be aligned to 2MiB (0x200000).
Load the Dump-capture Kernel
============================
@@ -334,6 +343,8 @@ For s390x:
- Use image or bzImage
For arm:
- Use zImage
For arm64:
- Use vmlinux or Image
If you are using a uncompressed vmlinux image then use following command
to load dump-capture kernel.
@@ -377,6 +388,9 @@ For s390x:
For arm:
"1 maxcpus=1 reset_devices"
For arm64:
"1 maxcpus=1 reset_devices"
Notes on loading the dump-capture kernel:
* By default, the ELF headers are stored in ELF64 format to support

7
Documentation/kernel-parameters.txt
View File

@@ -3590,6 +3590,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
spia_pedr=
spia_peddr=
stack_guard_gap= [MM]
override the default stack gap protection. The value
is in page units and it defines how many pages prior
to (for stacks growing down) resp. after (for stacks
growing up) the main stack are reserved for no other
mapping. Default value is 256 pages.
stacktrace [FTRACE]
Enabled the stack tracer on boot up.

13
Documentation/networking/ip-sysctl.txt
View File

@@ -1413,11 +1413,20 @@ accept_ra_pinfo - BOOLEAN
Functional default: enabled if accept_ra is enabled.
disabled if accept_ra is disabled.
accept_ra_rt_info_min_plen - INTEGER
Minimum prefix length of Route Information in RA.
Route Information w/ prefix smaller than this variable shall
be ignored.
Functional default: 0 if accept_ra_rtr_pref is enabled.
-1 if accept_ra_rtr_pref is disabled.
accept_ra_rt_info_max_plen - INTEGER
Maximum prefix length of Route Information in RA.
Route Information w/ prefix larger than or equal to this
variable shall be ignored.
Route Information w/ prefix larger than this variable shall
be ignored.
Functional default: 0 if accept_ra_rtr_pref is enabled.
-1 if accept_ra_rtr_pref is disabled.

332
Documentation/networking/netlink_mmap.txt
View File

@@ -1,332 +0,0 @@
This file documents how to use memory mapped I/O with netlink.
Author: Patrick McHardy <kaber@trash.net>
Overview
--------
Memory mapped netlink I/O can be used to increase throughput and decrease
overhead of unicast receive and transmit operations. Some netlink subsystems
require high throughput, these are mainly the netfilter subsystems
nfnetlink_queue and nfnetlink_log, but it can also help speed up large
dump operations of f.i. the routing database.
Memory mapped netlink I/O used two circular ring buffers for RX and TX which
are mapped into the processes address space.
The RX ring is used by the kernel to directly construct netlink messages into
user-space memory without copying them as done with regular socket I/O,
additionally as long as the ring contains messages no recvmsg() or poll()
syscalls have to be issued by user-space to get more message.
The TX ring is used to process messages directly from user-space memory, the
kernel processes all messages contained in the ring using a single sendmsg()
call.
Usage overview
--------------
In order to use memory mapped netlink I/O, user-space needs three main changes:
- ring setup
- conversion of the RX path to get messages from the ring instead of recvmsg()
- conversion of the TX path to construct messages into the ring
Ring setup is done using setsockopt() to provide the ring parameters to the
kernel, then a call to mmap() to map the ring into the processes address space:
- setsockopt(fd, SOL_NETLINK, NETLINK_RX_RING, &params, sizeof(params));
- setsockopt(fd, SOL_NETLINK, NETLINK_TX_RING, &params, sizeof(params));
- ring = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0)
Usage of either ring is optional, but even if only the RX ring is used the
mapping still needs to be writable in order to update the frame status after
processing.
Conversion of the reception path involves calling poll() on the file
descriptor, once the socket is readable the frames from the ring are
processed in order until no more messages are available, as indicated by
a status word in the frame header.
On kernel side, in order to make use of memory mapped I/O on receive, the
originating netlink subsystem needs to support memory mapped I/O, otherwise
it will use an allocated socket buffer as usual and the contents will be
copied to the ring on transmission, nullifying most of the performance gains.
Dumps of kernel databases automatically support memory mapped I/O.
Conversion of the transmit path involves changing message construction to
use memory from the TX ring instead of (usually) a buffer declared on the
stack and setting up the frame header appropriately. Optionally poll() can
be used to wait for free frames in the TX ring.
Structured and definitions for using memory mapped I/O are contained in
<linux/netlink.h>.
RX and TX rings
----------------
Each ring contains a number of continuous memory blocks, containing frames of
fixed size dependent on the parameters used for ring setup.
Ring: [ block 0 ]
[ frame 0 ]
[ frame 1 ]
[ block 1 ]
[ frame 2 ]
[ frame 3 ]
...
[ block n ]
[ frame 2 * n ]
[ frame 2 * n + 1 ]
The blocks are only visible to the kernel, from the point of view of user-space
the ring just contains the frames in a continuous memory zone.
The ring parameters used for setting up the ring are defined as follows:
struct nl_mmap_req {
unsigned int nm_block_size;
unsigned int nm_block_nr;
unsigned int nm_frame_size;
unsigned int nm_frame_nr;
};
Frames are grouped into blocks, where each block is a continuous region of memory
and holds nm_block_size / nm_frame_size frames. The total number of frames in
the ring is nm_frame_nr. The following invariants hold:
- frames_per_block = nm_block_size / nm_frame_size
- nm_frame_nr = frames_per_block * nm_block_nr
Some parameters are constrained, specifically:
- nm_block_size must be a multiple of the architectures memory page size.
The getpagesize() function can be used to get the page size.
- nm_frame_size must be equal or larger to NL_MMAP_HDRLEN, IOW a frame must be
able to hold at least the frame header
- nm_frame_size must be smaller or equal to nm_block_size
- nm_frame_size must be a multiple of NL_MMAP_MSG_ALIGNMENT
- nm_frame_nr must equal the actual number of frames as specified above.
When the kernel can't allocate physically continuous memory for a ring block,
it will fall back to use physically discontinuous memory. This might affect
performance negatively, in order to avoid this the nm_frame_size parameter
should be chosen to be as small as possible for the required frame size and
the number of blocks should be increased instead.
Ring frames
------------
Each frames contain a frame header, consisting of a synchronization word and some
meta-data, and the message itself.
Frame: [ header message ]
The frame header is defined as follows:
struct nl_mmap_hdr {
unsigned int nm_status;
unsigned int nm_len;
__u32 nm_group;
/* credentials */
__u32 nm_pid;
__u32 nm_uid;
__u32 nm_gid;
};
- nm_status is used for synchronizing processing between the kernel and user-
space and specifies ownership of the frame as well as the operation to perform
- nm_len contains the length of the message contained in the data area
- nm_group specified the destination multicast group of message
- nm_pid, nm_uid and nm_gid contain the netlink pid, UID and GID of the sending
process. These values correspond to the data available using SOCK_PASSCRED in
the SCM_CREDENTIALS cmsg.
The possible values in the status word are:
- NL_MMAP_STATUS_UNUSED:
RX ring: frame belongs to the kernel and contains no message
for user-space. Approriate action is to invoke poll()
to wait for new messages.
TX ring: frame belongs to user-space and can be used for
message construction.
- NL_MMAP_STATUS_RESERVED:
RX ring only: frame is currently used by the kernel for message
construction and contains no valid message yet.
Appropriate action is to invoke poll() to wait for
new messages.
- NL_MMAP_STATUS_VALID:
RX ring: frame contains a valid message. Approriate action is
to process the message and release the frame back to
the kernel by setting the status to
NL_MMAP_STATUS_UNUSED or queue the frame by setting the
status to NL_MMAP_STATUS_SKIP.
TX ring: the frame contains a valid message from user-space to
be processed by the kernel. After completing processing
the kernel will release the frame back to user-space by
setting the status to NL_MMAP_STATUS_UNUSED.
- NL_MMAP_STATUS_COPY:
RX ring only: a message is ready to be processed but could not be
stored in the ring, either because it exceeded the
frame size or because the originating subsystem does
not support memory mapped I/O. Appropriate action is
to invoke recvmsg() to receive the message and release
the frame back to the kernel by setting the status to
NL_MMAP_STATUS_UNUSED.
- NL_MMAP_STATUS_SKIP:
RX ring only: user-space queued the message for later processing, but
processed some messages following it in the ring. The
kernel should skip this frame when looking for unused
frames.
The data area of a frame begins at a offset of NL_MMAP_HDRLEN relative to the
frame header.
TX limitations
--------------
As of Jan 2015 the message is always copied from the ring frame to an
allocated buffer due to unresolved security concerns.
See commit 4682a0358639b29cf ("netlink: Always copy on mmap TX.").
Example
-------
Ring setup:
unsigned int block_size = 16 * getpagesize();
struct nl_mmap_req req = {
.nm_block_size = block_size,
.nm_block_nr = 64,
.nm_frame_size = 16384,
.nm_frame_nr = 64 * block_size / 16384,
};
unsigned int ring_size;
void *rx_ring, *tx_ring;
/* Configure ring parameters */
if (setsockopt(fd, SOL_NETLINK, NETLINK_RX_RING, &req, sizeof(req)) < 0)
exit(1);
if (setsockopt(fd, SOL_NETLINK, NETLINK_TX_RING, &req, sizeof(req)) < 0)
exit(1)
/* Calculate size of each individual ring */
ring_size = req.nm_block_nr * req.nm_block_size;
/* Map RX/TX rings. The TX ring is located after the RX ring */
rx_ring = mmap(NULL, 2 * ring_size, PROT_READ | PROT_WRITE,
MAP_SHARED, fd, 0);
if ((long)rx_ring == -1L)
exit(1);
tx_ring = rx_ring + ring_size:
Message reception:
This example assumes some ring parameters of the ring setup are available.
unsigned int frame_offset = 0;
struct nl_mmap_hdr *hdr;
struct nlmsghdr *nlh;
unsigned char buf[16384];
ssize_t len;
while (1) {
struct pollfd pfds[1];
pfds[0].fd = fd;
pfds[0].events = POLLIN | POLLERR;
pfds[0].revents = 0;
if (poll(pfds, 1, -1) < 0 && errno != -EINTR)
exit(1);
/* Check for errors. Error handling omitted */
if (pfds[0].revents & POLLERR)
<handle error>
/* If no new messages, poll again */
if (!(pfds[0].revents & POLLIN))
continue;
/* Process all frames */
while (1) {
/* Get next frame header */
hdr = rx_ring + frame_offset;
if (hdr->nm_status == NL_MMAP_STATUS_VALID) {
/* Regular memory mapped frame */
nlh = (void *)hdr + NL_MMAP_HDRLEN;
len = hdr->nm_len;
/* Release empty message immediately. May happen
* on error during message construction.
*/
if (len == 0)
goto release;
} else if (hdr->nm_status == NL_MMAP_STATUS_COPY) {
/* Frame queued to socket receive queue */
len = recv(fd, buf, sizeof(buf), MSG_DONTWAIT);
if (len <= 0)
break;
nlh = buf;
} else
/* No more messages to process, continue polling */
break;
process_msg(nlh);
release:
/* Release frame back to the kernel */
hdr->nm_status = NL_MMAP_STATUS_UNUSED;
/* Advance frame offset to next frame */
frame_offset = (frame_offset + frame_size) % ring_size;
}
}
Message transmission:
This example assumes some ring parameters of the ring setup are available.
A single message is constructed and transmitted, to send multiple messages
at once they would be constructed in consecutive frames before a final call
to sendto().
unsigned int frame_offset = 0;
struct nl_mmap_hdr *hdr;
struct nlmsghdr *nlh;
struct sockaddr_nl addr = {
.nl_family = AF_NETLINK,
};
hdr = tx_ring + frame_offset;
if (hdr->nm_status != NL_MMAP_STATUS_UNUSED)
/* No frame available. Use poll() to avoid. */
exit(1);
nlh = (void *)hdr + NL_MMAP_HDRLEN;
/* Build message */
build_message(nlh);
/* Fill frame header: length and status need to be set */
hdr->nm_len = nlh->nlmsg_len;
hdr->nm_status = NL_MMAP_STATUS_VALID;
if (sendto(fd, NULL, 0, 0, &addr, sizeof(addr)) < 0)
exit(1);
/* Advance frame offset to next frame */
frame_offset = (frame_offset + frame_size) % ring_size;

7
Documentation/sysctl/fs.txt
View File

@@ -265,6 +265,13 @@ aio-nr can grow to.
==============================================================
mount-max:
This denotes the maximum number of mounts that may exist
in a mount namespace.
==============================================================
2. /proc/sys/fs/binfmt_misc
----------------------------------------------------------

15
Documentation/sysctl/kernel.txt
View File

@@ -825,14 +825,13 @@ via the /proc/sys interface:
Each write syscall must fully contain the sysctl value to be
written, and multiple writes on the same sysctl file descriptor
will rewrite the sysctl value, regardless of file position.
0 - (default) Same behavior as above, but warn about processes that
perform writes to a sysctl file descriptor when the file position
is not 0.
1 - Respect file position when writing sysctl strings. Multiple writes
will append to the sysctl value buffer. Anything past the max length
of the sysctl value buffer will be ignored. Writes to numeric sysctl
entries must always be at file position 0 and the value must be
fully contained in the buffer sent in the write syscall.
0 - Same behavior as above, but warn about processes that perform writes
to a sysctl file descriptor when the file position is not 0.
1 - (default) Respect file position when writing sysctl strings. Multiple
writes will append to the sysctl value buffer. Anything past the max
length of the sysctl value buffer will be ignored. Writes to numeric
sysctl entries must always be at file position 0 and the value must
be fully contained in the buffer sent in the write syscall.
==============================================================

118
Documentation/tee.txt Normal file
View File

@@ -0,0 +1,118 @@
TEE subsystem
This document describes the TEE subsystem in Linux.
A TEE (Trusted Execution Environment) is a trusted OS running in some
secure environment, for example, TrustZone on ARM CPUs, or a separate
secure co-processor etc. A TEE driver handles the details needed to
communicate with the TEE.
This subsystem deals with:
- Registration of TEE drivers
- Managing shared memory between Linux and the TEE
- Providing a generic API to the TEE
The TEE interface
=================
include/uapi/linux/tee.h defines the generic interface to a TEE.
User space (the client) connects to the driver by opening /dev/tee[0-9]* or
/dev/teepriv[0-9]*.
- TEE_IOC_SHM_ALLOC allocates shared memory and returns a file descriptor
which user space can mmap. When user space doesn't need the file
descriptor any more, it should be closed. When shared memory isn't needed
any longer it should be unmapped with munmap() to allow the reuse of
memory.
- TEE_IOC_VERSION lets user space know which TEE this driver handles and
the its capabilities.
- TEE_IOC_OPEN_SESSION opens a new session to a Trusted Application.
- TEE_IOC_INVOKE invokes a function in a Trusted Application.
- TEE_IOC_CANCEL may cancel an ongoing TEE_IOC_OPEN_SESSION or TEE_IOC_INVOKE.
- TEE_IOC_CLOSE_SESSION closes a session to a Trusted Application.
There are two classes of clients, normal clients and supplicants. The latter is
a helper process for the TEE to access resources in Linux, for example file
system access. A normal client opens /dev/tee[0-9]* and a supplicant opens
/dev/teepriv[0-9].
Much of the communication between clients and the TEE is opaque to the
driver. The main job for the driver is to receive requests from the
clients, forward them to the TEE and send back the results. In the case of
supplicants the communication goes in the other direction, the TEE sends
requests to the supplicant which then sends back the result.
OP-TEE driver
=============
The OP-TEE driver handles OP-TEE [1] based TEEs. Currently it is only the ARM
TrustZone based OP-TEE solution that is supported.
Lowest level of communication with OP-TEE builds on ARM SMC Calling
Convention (SMCCC) [2], which is the foundation for OP-TEE's SMC interface
[3] used internally by the driver. Stacked on top of that is OP-TEE Message
Protocol [4].
OP-TEE SMC interface provides the basic functions required by SMCCC and some
additional functions specific for OP-TEE. The most interesting functions are:
- OPTEE_SMC_FUNCID_CALLS_UID (part of SMCCC) returns the version information
which is then returned by TEE_IOC_VERSION
- OPTEE_SMC_CALL_GET_OS_UUID returns the particular OP-TEE implementation, used
to tell, for instance, a TrustZone OP-TEE apart from an OP-TEE running on a
separate secure co-processor.
- OPTEE_SMC_CALL_WITH_ARG drives the OP-TEE message protocol
- OPTEE_SMC_GET_SHM_CONFIG lets the driver and OP-TEE agree on which memory
range to used for shared memory between Linux and OP-TEE.
The GlobalPlatform TEE Client API [5] is implemented on top of the generic
TEE API.
Picture of the relationship between the different components in the
OP-TEE architecture.
User space Kernel Secure world
~~~~~~~~~~ ~~~~~~ ~~~~~~~~~~~~
+--------+ +-------------+
| Client | | Trusted |
+--------+ | Application |
/\ +-------------+
|| +----------+ /\
|| |tee- | ||
|| |supplicant| \/
|| +----------+ +-------------+
\/ /\ | TEE Internal|
+-------+ || | API |
+ TEE | || +--------+--------+ +-------------+
| Client| || | TEE | OP-TEE | | OP-TEE |
| API | \/ | subsys | driver | | Trusted OS |
+-------+----------------+----+-------+----+-----------+-------------+
| Generic TEE API | | OP-TEE MSG |
| IOCTL (TEE_IOC_*) | | SMCCC (OPTEE_SMC_CALL_*) |
+-----------------------------+ +------------------------------+
RPC (Remote Procedure Call) are requests from secure world to kernel driver
or tee-supplicant. An RPC is identified by a special range of SMCCC return
values from OPTEE_SMC_CALL_WITH_ARG. RPC messages which are intended for the
kernel are handled by the kernel driver. Other RPC messages will be forwarded to
tee-supplicant without further involvement of the driver, except switching
shared memory buffer representation.
References:
[1] https://github.com/OP-TEE/optee_os
[2] http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
[3] drivers/tee/optee/optee_smc.h
[4] drivers/tee/optee/optee_msg.h
[5] http://www.globalplatform.org/specificationsdevice.asp look for
"TEE Client API Specification v1.0" and click download.

20
MAINTAINERS
View File

@@ -7830,6 +7830,13 @@ M: Harald Welte <laforge@gnumonks.org>
S: Maintained
F: drivers/char/pcmcia/cm4040_cs.*
OMNIVISION OV5647 SENSOR DRIVER
M: Ramiro Oliveira <roliveir@synopsys.com>
L: linux-media@vger.kernel.org
T: git git://linuxtv.org/media_tree.git
S: Maintained
F: drivers/media/i2c/ov5647.c
OMNIVISION OV7670 SENSOR DRIVER
M: Jonathan Corbet <corbet@lwn.net>
L: linux-media@vger.kernel.org
@@ -7939,6 +7946,11 @@ F: arch/*/oprofile/
F: drivers/oprofile/
F: include/linux/oprofile.h
OP-TEE DRIVER
M: Jens Wiklander <jens.wiklander@linaro.org>
S: Maintained
F: drivers/tee/optee/
ORACLE CLUSTER FILESYSTEM 2 (OCFS2)
M: Mark Fasheh <mfasheh@suse.com>
M: Joel Becker <jlbec@evilplan.org>
@@ -9366,6 +9378,14 @@ F: drivers/hwtracing/stm/
F: include/linux/stm.h
F: include/uapi/linux/stm.h
TEE SUBSYSTEM
M: Jens Wiklander <jens.wiklander@linaro.org>
S: Maintained
F: include/linux/tee_drv.h
F: include/uapi/linux/tee.h
F: drivers/tee/
F: Documentation/tee.txt
THUNDERBOLT DRIVER
M: Andreas Noever <andreas.noever@gmail.com>
S: Maintained

35
Makefile
View File

@@ -1,6 +1,6 @@
VERSION = 4
PATCHLEVEL = 4
SUBLEVEL = 55
SUBLEVEL = 83
EXTRAVERSION =
NAME = Blurry Fish Butt
@@ -146,7 +146,7 @@ PHONY += $(MAKECMDGOALS) sub-make
$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
@:
sub-make: FORCE
sub-make:
$(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \
-f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
@@ -636,6 +636,9 @@ include arch/$(SRCARCH)/Makefile
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
KBUILD_CFLAGS += $(call cc-disable-warning,maybe-uninitialized,)
KBUILD_CFLAGS += $(call cc-disable-warning,frame-address,)
KBUILD_CFLAGS += $(call cc-disable-warning, format-truncation)
KBUILD_CFLAGS += $(call cc-disable-warning, format-overflow)
KBUILD_CFLAGS += $(call cc-disable-warning, int-in-bool-context)
ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
KBUILD_CFLAGS += -Os
@@ -650,6 +653,17 @@ endif
# Tell gcc to never replace conditional load with a non-conditional one
KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0)
# check for 'asm goto'
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC) $(KBUILD_CFLAGS)), y)
KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
else ifneq ($(findstring aarch64-linux-android, $(CROSS_COMPILE)),)
# It seems than android gcc can't pass gcc-goto.sh check, but asm goto work.
# So let's active it.
KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
endif
ifdef CONFIG_READABLE_ASM
# Disable optimizations that make assembler listings hard to read.
# reorder blocks reorders the control in the function
@@ -805,17 +819,6 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
# use the deterministic mode of AR if available
KBUILD_ARFLAGS := $(call ar-option,D)
# check for 'asm goto'
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC)), y)
KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
else ifneq ($(findstring aarch64-linux-android, $(CROSS_COMPILE)),)
# It seems than android gcc can't pass gcc-goto.sh check, but asm goto work.
# So let's active it.
KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
KBUILD_AFLAGS += -DCC_HAVE_ASM_GOTO
endif
include scripts/Makefile.kasan
include scripts/Makefile.extrawarn
@@ -1022,7 +1025,7 @@ prepare1: prepare2 $(version_h) include/generated/utsrelease.h \
archprepare: archheaders archscripts prepare1 scripts_basic
prepare0: archprepare FORCE
prepare0: archprepare
$(Q)$(MAKE) $(build)=.
# All the preparing..
@@ -1067,7 +1070,7 @@ INSTALL_FW_PATH=$(INSTALL_MOD_PATH)/lib/firmware
export INSTALL_FW_PATH
PHONY += firmware_install
firmware_install: FORCE
firmware_install:
@mkdir -p $(objtree)/firmware
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_install
@@ -1087,7 +1090,7 @@ PHONY += archscripts
archscripts:
PHONY += __headers
__headers: $(version_h) scripts_basic asm-generic archheaders archscripts FORCE
__headers: $(version_h) scripts_basic asm-generic archheaders archscripts
$(Q)$(MAKE) $(build)=scripts build_unifdef
PHONY += headers_install_all

5
android/configs/android-base-arm64.cfg Normal file
View File

@@ -0,0 +1,5 @@
# KEEP ALPHABETICALLY SORTED
CONFIG_ARMV8_DEPRECATED=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y
CONFIG_SWP_EMULATION=y

42
android/configs/android-base.cfg
View File

@@ -1,31 +1,31 @@
# KEEP ALPHABETICALLY SORTED
# CONFIG_DEVKMEM is not set
# CONFIG_DEVMEM is not set
# CONFIG_FHANDLE is not set
# CONFIG_INET_LRO is not set
# CONFIG_MODULES is not set
# CONFIG_NFSD is not set
# CONFIG_NFS_FS is not set
# CONFIG_OABI_COMPAT is not set
# CONFIG_SYSVIPC is not set
# CONFIG_USELIB is not set
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_DEVICES=binder,hwbinder,vndbinder
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_ASHMEM=y
CONFIG_AUDIT=y
CONFIG_BLK_DEV_DM=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CGROUPS=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_SCHED=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_DM_CRYPT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DEFAULT_SECURITY_SELINUX=y
CONFIG_EMBEDDED=y
CONFIG_FB=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
@@ -42,7 +42,6 @@ CONFIG_IPV6=y
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IP_ADVANCED_ROUTER=y
@@ -64,10 +63,12 @@ CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_TPROXY=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
@@ -83,7 +84,6 @@ CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
@@ -139,11 +139,6 @@ CONFIG_PPP_DEFLATE=y
CONFIG_PPP_MPPE=y
CONFIG_PREEMPT=y
CONFIG_PROFILING=y
CONFIG_QFMT_V2=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_QUOTA_TREE=y
CONFIG_QUOTACTL=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RTC_CLASS=y
CONFIG_RT_GROUP_SCHED=y
@@ -152,21 +147,18 @@ CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
CONFIG_SECURITY_SELINUX=y
CONFIG_SETEND_EMULATION=y
CONFIG_STAGING=y
CONFIG_SWP_EMULATION=y
CONFIG_SYNC=y
CONFIG_TUN=y
CONFIG_UID_CPUTIME=y
CONFIG_UID_SYS_STATS=y
CONFIG_UNIX=y
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_MTP=y
CONFIG_USB_CONFIGFS_F_PTP=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_OTG_WAKELOCK=y
CONFIG_USB_CONFIGFS_F_MTP=y
CONFIG_USB_CONFIGFS_F_PTP=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_GADGET=y
CONFIG_XFRM_USER=y

14
android/configs/android-recommended.cfg
View File

@@ -7,16 +7,21 @@
# CONFIG_PM_WAKELOCKS_GC is not set
# CONFIG_VT is not set
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ARM_KERNMEM_PERMS=y
CONFIG_ARM64_SW_TTBR0_PAN=y
CONFIG_ARM_KERNMEM_PERMS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BLK_DEV_DM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_CC_STACKPROTECTOR_STRONG=y
CONFIG_COMPACTION=y
CONFIG_CPU_SW_DOMAIN_PAN=y
CONFIG_DEBUG_RODATA=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DRAGONRISE_FF=y
CONFIG_ENABLE_DEFAULT_TRACERS=y
CONFIG_EXT4_FS=y
@@ -92,6 +97,7 @@ CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGITECH_FF=y
CONFIG_MD=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEMORY_STATE_TIME=y
CONFIG_MSDOS_FS=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_PANTHERLORD_FF=y
@@ -103,6 +109,11 @@ CONFIG_POWER_SUPPLY=y
CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_RAM=y
CONFIG_QFMT_V2=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_QUOTA_TREE=y
CONFIG_SCHEDSTATS=y
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_SND=y
@@ -121,7 +132,6 @@ CONFIG_TIMER_STATS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_UHID=y
CONFIG_MEMORY_STATE_TIME=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HIDDEV=y

4
arch/Kconfig
View File

@@ -225,8 +225,8 @@ config ARCH_INIT_TASK
config ARCH_TASK_STRUCT_ALLOCATOR
bool
# Select if arch has its private alloc_thread_info() function
config ARCH_THREAD_INFO_ALLOCATOR
# Select if arch has its private alloc_thread_stack() function
config ARCH_THREAD_STACK_ALLOCATOR
bool
# Select if arch wants to size task_struct dynamically via arch_task_struct_size:

2
arch/alpha/kernel/module.c
View File

@@ -160,7 +160,7 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
/* The small sections were sorted to the end of the segment.
The following should definitely cover them. */
gp = (u64)me->module_core + me->core_size - 0x8000;
gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000;
got = sechdrs[me->arch.gotsecindex].sh_addr;
for (i = 0; i < n; i++) {

6
arch/alpha/kernel/osf_sys.c
View File

@@ -1188,8 +1188,10 @@ SYSCALL_DEFINE4(osf_wait4, pid_t, pid, int __user *, ustatus, int, options,
if (!access_ok(VERIFY_WRITE, ur, sizeof(*ur)))
return -EFAULT;
err = 0;
err |= put_user(status, ustatus);
err = put_user(status, ustatus);
if (ret < 0)
return err ? err : ret;
err |= __put_user(r.ru_utime.tv_sec, &ur->ru_utime.tv_sec);
err |= __put_user(r.ru_utime.tv_usec, &ur->ru_utime.tv_usec);
err |= __put_user(r.ru_stime.tv_sec, &ur->ru_stime.tv_sec);

2
arch/arc/include/asm/entry-arcv2.h
View File

@@ -16,6 +16,7 @@
;
; Now manually save: r12, sp, fp, gp, r25
PUSH r30
PUSH r12
; Saving pt_regs->sp correctly requires some extra work due to the way
@@ -72,6 +73,7 @@
POPAX AUX_USER_SP
1:
POP r12
POP r30
.endm

2
arch/arc/include/asm/ptrace.h
View File

@@ -84,7 +84,7 @@ struct pt_regs {
unsigned long fp;
unsigned long sp; /* user/kernel sp depending on where we came from */
unsigned long r12;
unsigned long r12, r30;
/*------- Below list auto saved by h/w -----------*/
unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;

4
arch/arc/kernel/unwind.c
View File

@@ -385,8 +385,8 @@ void *unwind_add_table(struct module *module, const void *table_start,
return NULL;
init_unwind_table(table, module->name,
module->module_core, module->core_size,
module->module_init, module->init_size,
module->core_layout.base, module->core_layout.size,
module->init_layout.base, module->init_layout.size,
table_start, table_size,
NULL, 0);

2
arch/arc/mm/mmap.c
View File

@@ -64,7 +64,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
vma = find_vma(mm, addr);
if (TASK_SIZE - len >= addr &&
(!vma || addr + len <= vma->vm_start))
(!vma || addr + len <= vm_start_gap(vma)))
return addr;
}

9
arch/arm/boot/compressed/Makefile
View File

@@ -106,6 +106,15 @@ ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
endif
# -fstack-protector-strong triggers protection checks in this code,
# but it is being used too early to link to meaningful stack_chk logic.
nossp_flags := $(call cc-option, -fno-stack-protector)
CFLAGS_atags_to_fdt.o := $(nossp_flags)
CFLAGS_fdt.o := $(nossp_flags)
CFLAGS_fdt_ro.o := $(nossp_flags)
CFLAGS_fdt_rw.o := $(nossp_flags)
CFLAGS_fdt_wip.o := $(nossp_flags)
ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
asflags-y := -DZIMAGE

15
arch/arm/boot/dts/Makefile
View File

@@ -517,18 +517,26 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
rk3126-evb.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-echo-v10.dtb \
rk3229-evb.dtb \
rk3229-gva-sdk.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-android-act8846-edp.dtb \
rk3288-evb-android-rk818-edp.dtb \
rk3288-evb-android-rk818-lvds.dtb \
rk3288-evb-android-rk818-mipi.dtb \
rk3288-evb-rk808.dtb \
rk3288-evb-rk818-edp.dtb \
rk3288-evb-rk818-mipi.dtb \
rk3288-fennec.dtb \
rk3288-firefly-beta.dtb \
rk3288-firefly-reload.dtb \
rk3288-firefly-rk808.dtb \
rk3288-firefly.dtb \
rk3288-miniarm.dtb \
rk3288-miqi.dtb \
rk3288-phycore-rdk.dtb \
rk3288-popmetal.dtb \
rk3288-r89.dtb \
rk3288-rock2-square.dtb \
@@ -536,7 +544,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb
rk3288-veyron-speedy.dtb \
rk3288-x7811-rk818-dual-dsi.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \

4
arch/arm/boot/dts/armada-388-gp.dts
View File

@@ -89,7 +89,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pca0_pins>;
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -101,7 +101,7 @@
compatible = "nxp,pca9555";
pinctrl-names = "default";
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;

5
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@@ -162,9 +162,10 @@
};
adc0: adc@f8018000 {
atmel,adc-vref = <3300>;
atmel,adc-channels-used = <0xfe>;
pinctrl-0 = <
&pinctrl_adc0_adtrg
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
@@ -172,8 +173,6 @@
&pinctrl_adc0_ad5
&pinctrl_adc0_ad6
&pinctrl_adc0_ad7
&pinctrl_adc0_ad8
&pinctrl_adc0_ad9
>;
status = "okay";
};

4
arch/arm/boot/dts/bcm5301x.dtsi
View File

@@ -54,14 +54,14 @@
timer@0200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x0200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&clk_periph>;
};
local-timer@0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x0600 0x100>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
clocks = <&clk_periph>;
};

2
arch/arm/boot/dts/imx6dl.dtsi
View File

@@ -30,7 +30,7 @@
/* kHz uV */
996000 1250000
792000 1175000
396000 1075000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */

2
arch/arm/boot/dts/omap3-n900.dts
View File

@@ -697,6 +697,8 @@
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
};
&mmc3 {

2
arch/arm/boot/dts/rk3036-kylin.dts
View File

@@ -357,6 +357,8 @@
reg = <0x1b>;
clocks = <&cru SCLK_I2S_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s_mclk>;
#sound-dai-cells = <0>;
};
};

7
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -775,13 +775,16 @@
i2s {
i2s_bus: i2s-bus {
rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
<1 1 RK_FUNC_1 &pcfg_pull_default>,
rockchip,pins = <1 1 RK_FUNC_1 &pcfg_pull_default>,
<1 2 RK_FUNC_1 &pcfg_pull_default>,
<1 3 RK_FUNC_1 &pcfg_pull_default>,
<1 4 RK_FUNC_1 &pcfg_pull_default>,
<1 5 RK_FUNC_1 &pcfg_pull_default>;
};
i2s_mclk: i2s-mclk {
rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>;
};
};
hdmi {

465
arch/arm/boot/dts/rk3126-evb.dts Normal file
View File

@@ -0,0 +1,465 @@
/*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3126.dtsi"
#include "rk312x-android.dtsi"
/ {
model = "Rockchip RK3126 Evaluation board";
compatible = "rockchip,rk3126";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <3300000>;
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <0>;
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <1650000>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
enable-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
};
lvds_panel: lvds-panel {
status = "disabled";
ports {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "SARADC_AVDD33";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <4000000>;
regulator-always-on;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
status = "okay";
route {
route_lvds: route-lvds {
status = "okay";
};
};
};
&dmc {
center-supply = <&vdd_log>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gpu {
status = "okay";
mali-supply = <&vdd_log>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
rk816: pmic@1a {
compatible = "rockchip,rk816";
reg = <0x1a>;
interrupt-parent = <&gpio0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk816-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_sys>;
gpio {
status = "okay";
};
pwrkey {
status = "okay";
};
rtc {
status = "okay";
};
regulators {
vdd_arm: DCDC_REG1{
regulator-name= "vdd_arm";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_log: DCDC_REG2 {
regulator-name= "vdd_logic";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc28_cif: LDO_REG1 {
regulator-name = "vcc28_cif";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc18_cif: LDO_REG2 {
regulator-name = "vcc18_cif";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_11: LDO_REG3 {
regulator-name = "vdd_11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1100000>;
};
};
ldo4: LDO_REG4 {
regulator-name= "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo5: LDO_REG5 {
regulator-name= "ldo5";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
ldo6: LDO_REG6 {
regulator-name= "ldo6";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
};
};
};
&lvds {
status = "okay";
pinctrl-names = "lcdc";
pinctrl-0 = <&lcdc_lcdc>;
ports {
lvds_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
lvds_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&lvds_panel {
status = "okay";
compatible ="simple-panel";
backlight = <&backlight>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
/* enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
* delay,disable = <10>;
* power-supply = <&vcc_lcd>;
*/
power-supply = <&ldo6>;
power-invert = <1>;
rockchip,data-mapping = "jeida";
rockchip,data-width = <18>;
rockchip,output = "rgb";
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <60000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <100>;
hfront-porch = <120>;
vback-porch = <10>;
vfront-porch = <15>;
hsync-len = <100>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
&pinctrl {
lcdc {
lcdc_lcdc: lcdc-lcdc {
rockchip,pins =
/* depend on the hardware */
<2 RK_PB0 1 &pcfg_pull_none>, /* DCLK */
/* <2 RK_PB1 1 &pcfg_pull_none>, /* HSYNC */
/* <2 RK_PB2 1 &pcfg_pull_none>, /* VSYNC */
<2 RK_PB3 1 &pcfg_pull_none>, /* DEN */
<2 RK_PB4 1 &pcfg_pull_none>, /* DATA10 */
<2 RK_PB5 1 &pcfg_pull_none>, /* DATA11 */
<2 RK_PB6 1 &pcfg_pull_none>, /* DATA12 */
<2 RK_PB7 1 &pcfg_pull_none>, /* DATA13 */
<2 RK_PC0 1 &pcfg_pull_none>, /* DATA14 */
<2 RK_PC1 1 &pcfg_pull_none>, /* DATA15 */
<2 RK_PC2 1 &pcfg_pull_none>, /* DATA16 */
<2 RK_PC3 1 &pcfg_pull_none>; /* DATA17 */
/* <2 RK_PC4 1 &pcfg_pull_none>, /* DATA18 */
/* <2 RK_PC5 1 &pcfg_pull_none>, /* DATA19 */
/* <2 RK_PC6 1 &pcfg_pull_none>, /* DATA20 */
/* <2 RK_PC7 1 &pcfg_pull_none>, /* DATA21 */
/* <2 RK_PD0 1 &pcfg_pull_none>, /* DATA22 */
/* <2 RK_PD1 1 &pcfg_pull_none>; /* DATA23 */
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vccadc_ref>;
};
&sdmmc {
cap-mmc-highspeed;
supports-sd;
broken-cd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* CD GPIO */
status = "disabled";
};
&sdio {
cap-mmc-highspeed;
supports-sdio;
ignore-pm-notify;
keep-power-in-suspend;
non-removable;
cap-sdio-irq;
status = "disabled";
};
&u2phy {
status = "okay";
u2phy_otg: otg-port {
status = "okay";
};
u2phy_host: host-port {
status = "okay";
};
};
&usb_otg {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

89
arch/arm/boot/dts/rk3126.dtsi
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@@ -1,44 +1,53 @@
/*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "rk312x.dtsi"
&clk_gpll_div2 {
clocks = <&dummy>;
};
/ {
compatible = "rockchip,rk3126";
&clk_gpll_div3 {
clocks = <&dummy>;
};
&aclk_vio0_pre_div {
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
&aclk_vio1_pre_div {
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
&hclk_vio_pre_div {
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
&rockchip_clocks_init {
rockchip,clocks-init-parent =
<&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
<&aclk_peri &clk_gpll>, <&clk_uart0_pll &clk_gpll>,
<&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
<&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
<&clk_vepu &clk_gpll>, <&clk_vdpu &clk_gpll>,
<&clk_hevc_core &clk_gpll>,
<&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll>,
<&clk_cif_pll &clk_gpll>, <&dclk_ebc &clk_gpll>,
<&clk_emmc &clk_gpll>, <&clk_sdio &clk_gpll>,
<&clk_sfc &clk_gpll>, <&clk_sdmmc0 &clk_gpll>,
<&clk_tsp &clk_gpll>, <&clk_nandc &clk_gpll>,
<&clk_mac_pll &clk_cpll>;
};
&i2s0 {
/* sdi: 0: from io, 1: from acodec */
sdi_source = <1>;
status = "okay";
cru: clock-controller@20000000 {
compatible = "rockchip,rk3126-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

72
arch/arm/boot/dts/rk3128-dram-default-timing.dtsi Normal file
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/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/rk3128-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <DDR3_DEFAULT>;
pd_idle = <0x40>;
sr_idle = <0x1>;
auto_pd_dis_freq = <300>;
auto_sr_dis_freq = <300>;
ddr3_dll_dis_freq = <300>;
lpddr2_dll_dis_freq = <300>;
phy_dll_dis_freq = <266>;
ddr3_odt_dis_freq = <333>;
phy_ddr3_odt_disb_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_clk_drv = <PHY_RON_44ohm>;
phy_ddr3_cmd_drv = <PHY_RON_44ohm>;
phy_ddr3_dqs_drv = <PHY_RON_44ohm>;
phy_ddr3_odt = <PHY_RTT_216ohm>;
lpddr2_drv = <LP2_DS_34ohm>;
phy_lpddr2_clk_drv = <PHY_RON_44ohm>;
phy_lpddr2_cmd_drv = <PHY_RON_44ohm>;
phy_lpddr2_dqs_drv = <PHY_RON_44ohm>;
};
};

52
arch/arm/boot/dts/rk3128.dtsi
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@@ -1 +1,53 @@
/*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "rk312x.dtsi"
/ {
compatible = "rockchip,rk3128";
cru: clock-controller@20000000 {
compatible = "rockchip,rk3128-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

155
arch/arm/boot/dts/rk312x-android.dtsi Normal file
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@@ -0,0 +1,155 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/soc/rockchip-system-status.h>
#include "rk3128-dram-default-timing.dtsi"
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0x20068000";
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&efuse_id>;
nvmem-cell-names = "id";
};
dfi: dfi {
compatible = "rockchip,rk3128-dfi";
rockchip,pmu = <&pmu>;
rockchip,grf = <&grf>;
status = "okay";
};
dmc: dmc {
compatible = "rockchip,rk3128-dmc";
devfreq-events = <&dfi>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
upthreshold = <55>;
downdifferential = <10>;
operating-points-v2 = <&dmc_opp_table>;
vop-dclk-mode = <0>;
min-cpu-freq = <600000>;
rockchip,ddr_timing = <&ddr_timing>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 456000
SYS_STATUS_SUSPEND 200000
>;
auto-min-freq = <300000>;
auto-freq-en = <0>;
status = "okay";
};
dmc_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <950000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000>;
};
opp-396000000 {
opp-hz = /bits/ 64 <396000000>;
opp-microvolt = <1100000>;
};
opp-456000000 {
opp-hz = /bits/ 64 <456000000>;
opp-microvolt = <1200000>;
};
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,signal-irq = <159>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ramoops_mem: ramoops@00000000 {
reg = <0x68000000 0xf0000>;
};
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
};
ramoops {
compatible = "ramoops";
record-size = <0x0 0x20000>;
console-size = <0x0 0x80000>;
ftrace-size = <0x0 0x00000>;
pmsg-size = <0x0 0x50000>;
memory-region = <&ramoops_mem>;
};
};
&display_subsystem {
memory-region = <&drm_logo>;
route {
route_lvds: route-lvds {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_lvds>;
};
};
};

1781
arch/arm/boot/dts/rk312x.dtsi Executable file → Normal file
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File diff suppressed because it is too large Load Diff

19
arch/arm/boot/dts/rk3228-evb.dts
View File

@@ -46,10 +46,17 @@
model = "Rockchip RK3228 Evaluation board";
compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
memory {
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&emmc {
@@ -61,6 +68,16 @@
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_SRC>;
assigned-clock-rates = <50000000>;
clock_in_out = "output";
phy-supply = <&vcc_phy>;
phy-mode = "rmii";
phy-is-integrated;
status = "okay";
};
&tsadc {
status = "okay";

88
arch/arm/boot/dts/rk3229-cpu-opp.dtsi Normal file
View File

@@ -0,0 +1,88 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
/delete-node/ opp-table0;
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1175000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1275000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1325000>;
};
opp-1392000000 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <1375000>;
};
opp-1464000000 {
opp-hz = /bits/ 64 <1464000000>;
opp-microvolt = <1400000>;
};
};
};

339
arch/arm/boot/dts/rk3229-echo-v10.dts Normal file
View File

@@ -0,0 +1,339 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk322x.dtsi"
#include "rk3229-cpu-opp.dtsi"
#include "rk322x-android.dtsi"
/ {
model = "RK3229 Echo Board V1.0";
compatible = "rockchip,rk3229-echo", "rockchip,rk3229";
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
trust_reserved: trust@0x68400000 {
reg = <0x68400000 0xe00000>;
no-map;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk805 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk805 1>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart11_rts>;
pinctrl-1 = <&uart11_rts_gpio>;
BT,reset_gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio3 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6255";
WIFI,host_wake_irq = <&gpio0 28 GPIO_ACTIVE_HIGH>;
status = "okay";
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power_key: power-key {
label = "GPIO Key Power";
gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
linux,code = <116>;
debounce-interval = <100>;
wakeup-source;
};
};
};
&gpu {
status = "okay";
mali-supply = <&vdd_logic>;
};
&i2c0 {
status = "okay";
rk805: rk805@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
rtc {
status = "okay";
};
pwrkey {
status = "okay";
};
gpio {
status = "okay";
};
regulators {
compatible = "rk805-regulator";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
vdd_arm: RK805_DCDC1@0 {
regulator-compatible = "RK805_DCDC1";
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_logic: RK805_DCDC2@1 {
regulator-compatible = "RK805_DCDC2";
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: RK805_DCDC3@2 {
regulator-compatible = "RK805_DCDC3";
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
};
};
vcc_io: RK805_DCDC4@3 {
regulator-compatible = "RK805_DCDC4";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: RK805_LDO1@4 {
regulator-compatible = "RK805_LDO1";
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: RK805_LDO2@5 {
regulator-compatible = "RK805_LDO2";
regulator-name = "vcc_18emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: RK805_LDO3@6 {
regulator-compatible = "RK805_LDO3";
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc_18>;
vccio4-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 12 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_b4 */
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
keys {
pwr_key: pwr-key {
rockchip,pins = <3 23 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdio {
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
num-slots = <1>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc_host>;
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};

284
arch/arm/boot/dts/rk3229-evb.dts
View File

@@ -1,4 +1,6 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
@@ -41,21 +43,115 @@
/dts-v1/;
#include "rk322x.dtsi"
#include "rk3229-cpu-opp.dtsi"
#include "rk322x-android.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
memory {
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power_key: power-key {
label = "GPIO Key Power";
gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <100>;
wakeup-source;
};
};
hdmi_sound: hdmi-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,hdmi";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vccio_1v8_reg: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "vccio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vccio_3v3_reg: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "vccio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
};
spdif_out: spdif-out {
status = "okay";
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
spdif-sound {
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,name = "ROCKCHIP,SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
};
vcc_phy: vcc-phy-regulator {
@@ -67,24 +163,176 @@
regulator-always-on;
regulator-boot-on;
};
vdd_arm: vdd-arm-regulator {
compatible = "pwm-regulator";
rockchip,pwm_id = <1>;
rockchip,pwm_voltage = <1100000>;
pwms = <&pwm1 0 25000 1>;
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-log-regulator {
compatible = "pwm-regulator";
rockchip,pwm_id = <2>;
rockchip,pwm_voltage = <1200000>;
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6335";
sdio_vref = <1800>;
WIFI,host_wake_irq = <&gpio0 28 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&gmac {
assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
clock_in_out = "input";
assigned-clocks = <&cru SCLK_MAC_SRC>;
assigned-clock-rates = <50000000>;
clock_in_out = "output";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
phy-mode = "rmii";
phy-is-integrated;
status = "okay";
};
&uart2 {
&gpu {
status = "okay";
mali-supply = <&vdd_log>;
};
&hdmi {
status = "okay";
#sound-dai-cells = <0>;
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
rockchip,phy_table =
<165000000 0 0 4 4 4 4>,
<225000000 0 0 6 6 6 6>,
<340000000 1 0 6 10 10 10>,
<594000000 1 0 7 10 10 10>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vccio_3v3_reg>;
vccio2-supply = <&vccio_1v8_reg>;
vccio4-supply = <&vccio_3v3_reg>;
};
&i2c0 {
status = "okay";
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&i2s0 {
status = "okay";
rockchip,bclk-fs = <128>;
#sound-dai-cells = <0>;
};
&pinctrl {
keys {
pwr_key: pwr-key {
rockchip,pins = <3 23 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <1 14 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&sdio {
status = "okay";
mmc-pwrseq = <&sdio_pwrseq>;
};
&sdmmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr &sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
};
&spdif {
status = "okay";
#sound-dai-cells = <0>;
};
&u2phy0_host {
phy-supply = <&vcc_host>;
};
&u2phy1_host {
phy-supply = <&vcc_host>;
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host2_ehci {
status = "okay";
};
&usb_host2_ohci {
status = "okay";
};

360
arch/arm/boot/dts/rk3229-gva-sdk.dts Normal file
View File

@@ -0,0 +1,360 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk322x.dtsi"
#include "rk3229-cpu-opp.dtsi"
#include "rk322x-android.dtsi"
/ {
model = "RK3229 GOOGLE VOICE ASSISTANT SDK Board";
compatible = "rockchip,rk3229-gva-sdk", "rockchip,rk3229";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk805 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk805 1>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart11_rts>;
pinctrl-1 = <&uart11_rts_gpio>;
BT,reset_gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio3 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6255";
WIFI,host_wake_irq = <&gpio0 28 GPIO_ACTIVE_HIGH>;
status = "okay";
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key &bt_key &mute_key>;
power_key {
label = "GPIO Key Power";
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
linux,code = <116>;
debounce-interval = <100>;
wakeup-source;
};
bt_key {
label = "Blutooth Key";
gpios = <&gpio3 31 GPIO_ACTIVE_HIGH>;
linux,code = <237>;
debounce-interval = <100>;
};
mute_key {
label = "Mute Key";
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
linux,code = <113>;
debounce-interval = <100>;
};
};
};
&gpu {
status = "okay";
mali-supply = <&vdd_logic>;
};
&nandc {
status = "disabled";
};
&emmc {
status = "okay";
};
&i2c0 {
status = "okay";
rk805: rk805@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
spinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
rtc {
status = "okay";
};
pwrkey {
status = "okay";
};
gpio {
status = "okay";
};
regulators {
compatible = "rk805-regulator";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
vdd_arm: RK805_DCDC1@0 {
regulator-compatible = "RK805_DCDC1";
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_logic: RK805_DCDC2@1 {
regulator-compatible = "RK805_DCDC2";
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: RK805_DCDC3@2 {
regulator-compatible = "RK805_DCDC3";
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
};
};
vcc_io: RK805_DCDC4@3 {
regulator-compatible = "RK805_DCDC4";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: RK805_LDO1@4 {
regulator-compatible = "RK805_LDO1";
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: RK805_LDO2@5 {
regulator-compatible = "RK805_LDO2";
regulator-name = "vcc_18emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: RK805_LDO3@6 {
regulator-compatible = "RK805_LDO3";
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&i2c1 {
status = "okay";
ts@8 {
compatible = "cypress,cy8c4024";
reg = <0x8>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
&i2c2 {
status = "okay";
cw2015@62 {
status = "okay";
compatible = "cw201x";
reg = <0x62>;
bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 0x48 0x44 0x44 0x46 0x49 0x48 0x32
0x24 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E 0x4D 0x52 0x52
0x57 0x3D 0x1B 0x6A 0x2D 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB
0xCB 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>;
monitor_sec = <5>;
virtual_power = <0>;
divider_res1 = <200>;
divider_res2 = <200>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc_18>;
vccio4-supply = <&vcc_io>;
};
&pinctrl {
keys {
pwr_key: pwr-key {
rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_key: bt-key {
rockchip,pins = <3 31 RK_FUNC_GPIO &pcfg_pull_down>;
};
mute_key: mute-key {
rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 12 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_b4 */
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio {
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
num-slots = <1>;
sd-uhs-sdr104;
status = "okay";
};
&rockchip_suspend {
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_GTCLKS
|RKPM_CTR_IDLESRAM_MD
|RKPM_CTR_PMIC
)
>;
};

184
arch/arm/boot/dts/rk322x-android.dtsi Normal file
View File

@@ -0,0 +1,184 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0x11030000";
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,signal-irq = <159>;
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
pinctrl-names = "default";
pinctrl-0 = <&uart21_xfer>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
/delete-property/ default-sample-phase;
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_phy {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
max-frequency = <50000000>;
num-slots = <1>;
supports-sd;
};
&sdio {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cap-sdio-irq;
non-removable;
ignore-pm-notify;
keep-power-in-suspend;
max-frequency = <150000000>;
supports-sdio;
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
status = "okay";
};
&u2phy0 {
otg-vbus-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
status = "okay";
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart11_xfer &uart11_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_otg {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP>;
assigned-clock-parents = <&cru HDMIPHY>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&rockchip_suspend {
status = "okay";
};

666
arch/arm/boot/dts/rk322x.dtsi
View File

@@ -43,6 +43,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/suspend/rockchip-rk322x.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
#include "skeleton.dtsi"
@@ -53,6 +55,7 @@
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
spi0 = &spi0;
};
cpus {
@@ -64,11 +67,9 @@
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
816000 1000000
>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <122>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
@@ -78,6 +79,7 @@
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@f02 {
@@ -85,6 +87,7 @@
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@f03 {
@@ -92,6 +95,38 @@
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1175000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1275000>;
};
};
@@ -109,6 +144,7 @@
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
peripherals-req-type-burst;
};
};
@@ -166,6 +202,20 @@
status = "disabled";
};
spdif: spdif@100d0000 {
compatible = "rockchip,rk3228-spdif";
reg = <0x100d0000 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
clock-names = "mclk", "hclk";
dmas = <&pdma 10>;
#dma-cells = <1>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
status = "disabled";
};
i2s2: i2s2@100e0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
@@ -180,8 +230,76 @@
};
grf: syscon@11000000 {
compatible = "syscon";
compatible = "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk322x-io-voltage-domain";
status = "disabled";
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x5c8>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-ums = <BOOT_UMS>;
};
u2phy0: usb2-phy@760 {
compatible = "rockchip,rk322x-usb2phy";
reg = <0x0760 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy0";
status = "disabled";
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
u2phy1: usb2-phy@800 {
compatible = "rockchip,rk322x-usb2phy";
reg = <0x0800 0x0c>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy1";
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
u2phy1_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
};
uart0: serial@11010000 {
@@ -220,12 +338,29 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
pinctrl-0 = <&uart21_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
efuse: efuse@11040000 {
compatible = "rockchip,rk322x-efuse";
reg = <0x11040000 0x20>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE_256>;
clock-names = "pclk_efuse";
/* Data cells */
efuse_id: id@7 {
reg = <0x7 0x10>;
};
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
};
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
@@ -278,6 +413,27 @@
status = "disabled";
};
spi0: spi@11090000 {
compatible = "rockchip,rk3228-spi";
reg = <0x11090000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
status = "disabled";
};
wdt: watchdog@110a0000 {
compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
reg = <0x110a0000 0x100>;
clocks = <&cru PCLK_CPU>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pwm0: pwm@110b0000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b0000 0x10>;
@@ -336,29 +492,40 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <594000000>;
assigned-clocks =
<&cru PLL_GPLL>, <&cru ARMCLK>,
<&cru PLL_CPLL>, <&cru ACLK_PERI>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
<&cru ACLK_CPU>, <&cru HCLK_CPU>,
<&cru PCLK_CPU>;
assigned-clock-rates =
<594000000>, <816000000>,
<500000000>, <150000000>,
<150000000>, <75000000>,
<150000000>, <150000000>,
<75000000>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
sustainable-power = <1200>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
threshold: trip-point@0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>; /* millicelsius */
target: trip-point@1 {
temperature = <85000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
soc_crit: soc-crit {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
@@ -367,14 +534,16 @@
cooling-maps {
map0 {
trip = <&cpu_alert0>;
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map1 {
trip = <&cpu_alert1>;
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
@@ -386,6 +555,8 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <32768>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
@@ -397,15 +568,237 @@
status = "disabled";
};
hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
#phy-cells = <0>;
clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>;
clock-names = "sysclk", "refclk";
#clock-cells = <0>;
clock-output-names = "hdmiphy_phy";
status = "disabled";
};
gpu: gpu@0x20001000 {
compatible = "arm,mali400";
reg = <0x20001000 0x200>,
<0x20000000 0x100>,
<0x20003000 0x100>,
<0x20008000 0x1100>,
<0x20004000 0x100>,
<0x2000A000 0x1100>,
<0x20005000 0x100>;
reg-names = "Mali_L2",
"Mali_GP",
"Mali_GP_MMU",
"Mali_PP0",
"Mali_PP0_MMU",
"Mali_PP1",
"Mali_PP1_MMU";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "Mali_GP_IRQ",
"Mali_GP_MMU_IRQ",
"Mali_PP0_IRQ",
"Mali_PP0_MMU_IRQ",
"Mali_PP1_IRQ",
"Mali_PP1_MMU_IRQ";
clocks = <&cru ACLK_GPU>;
#cooling-cells = <2>; /* min followed by max */
clock-names = "clk_mali";
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
gpu_power_model: power_model {
compatible = "arm,mali-simple-power-model";
voltage = <900>;
frequency = <500>;
static-power = <300>;
dynamic-power = <396>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
gpu_opp_table: opp-table2 {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1050000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1050000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1150000>;
};
};
vpu_service: vpu-service@20020000 {
compatible = "rockchip,vpu_service";
reg = <0x20020000 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>;
reset-names = "video_a", "video_h";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,grf = <&grf>;
iommus = <&vpu_mmu>;
allocator = <1>;
status = "disabled";
};
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x40>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clock-names = "aclk", "hclk";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
rkvdec: rkvdec@20030000 {
compatible = "rockchip,rkvdec";
reg = <0x20030000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac",
"clk_core";
resets = <&cru SRST_RKVDEC_A>, <&cru SRST_RKVDEC_H>,
<&cru SRST_RKVDEC_NOC_A>, <&cru SRST_RKVDEC_NOC_H>,
<&cru SRST_RKVDEC_CABAC>, <&cru SRST_RKVDEC_CORE>;
reset-names = "video_a", "video_h", "niu_a", "niu_h",
"cabac", "video";
rockchip,grf = <&grf>;
iommus = <&rkvdec_mmu>;
allocator = <1>;
status = "disabled";
};
rkvdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "hclk";
#iommu-cells = <0>;
status = "disabled";
};
vop: vop@20050000 {
compatible = "rockchip,rk322x-vop";
reg = <0x20050000 0x1ffc>;
reg-names = "regs";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
status = "disabled";
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
};
};
vop_mmu: iommu@20050300 {
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "hclk";
#iommu-cells = <0>;
status = "disabled";
};
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
hdmi: hdmi@200a0000 {
compatible = "rockchip,rk3228-dw-hdmi";
reg = <0x200a0000 0x20000>;
reg-io-width = <4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>;
clock-names = "isfr", "iahb";
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd>;
resets = <&cru SRST_HDMI_P>;
reset-names = "hdmi";
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
rockchip,grf = <&grf>;
status = "disabled";
port {
hdmi_in_vop: endpoint {
remote-endpoint = <&vop_out_hdmi>;
};
};
};
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "disabled";
};
sdio: dwmmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
status = "disabled";
};
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
clock-freq-min-max = <400000 37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
default-sample-phase = <158>;
num-slots = <1>;
@@ -415,6 +808,99 @@
status = "disabled";
};
nandc: nandc@30030000 {
compatible = "rockchip,rk-nandc";
reg = <0x30030000 0x4000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
nandc_id = <0>;
clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
clock-names = "clk_nandc", "hclk_nandc";
status = "disabled";
};
usb_otg: usb@30040000 {
compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x30040000 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host0_ehci: usb@30080000 {
compatible = "generic-ehci";
reg = <0x30080000 0x20000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
clock-names = "usbhost", "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
};
usb_host0_ohci: usb@300a0000 {
compatible = "generic-ohci";
reg = <0x300a0000 0x20000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
clock-names = "usbhost", "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
};
usb_host1_ehci: usb@300c0000 {
compatible = "generic-ehci";
reg = <0x300c0000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
clock-names = "usbhost", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
};
usb_host1_ohci: usb@300e0000 {
compatible = "generic-ohci";
reg = <0x300e0000 0x20000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
clock-names = "usbhost", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
};
usb_host2_ehci: usb@30100000 {
compatible = "generic-ehci";
reg = <0x30100000 0x20000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
phys = <&u2phy1_otg>;
phy-names = "usb";
clock-names = "usbhost", "utmi";
status = "disabled";
};
usb_host2_ohci: usb@30120000 {
compatible = "generic-ohci";
reg = <0x30120000 0x20000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
clock-names = "usbhost", "utmi";
phys = <&u2phy1_otg>;
phy-names = "usb";
status = "disabled";
};
gmac: ethernet@30200000 {
compatible = "rockchip,rk3228-gmac";
reg = <0x30200000 0x10000>;
@@ -423,13 +909,13 @@
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
<&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
resets = <&cru SRST_GMAC>;
reset-names = "stmmaceth";
"pclk_mac", "clk_macphy";
resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>;
reset-names = "stmmaceth", "mac-phy";
rockchip,grf = <&grf>;
status = "disabled";
};
@@ -522,6 +1008,40 @@
drive-strength = <12>;
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
@@ -581,6 +1101,17 @@
};
};
hdmi {
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_down>;
};
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 6 RK_FUNC_2 &pcfg_pull_none>,
<0 7 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
@@ -609,6 +1140,42 @@
};
};
spi-0 {
spi0_clk: spi0-clk {
rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi-1 {
spi1_clk: spi1-clk {
rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
@@ -617,9 +1184,9 @@
<0 12 RK_FUNC_1 &pcfg_pull_none>,
<0 13 RK_FUNC_1 &pcfg_pull_none>,
<0 14 RK_FUNC_1 &pcfg_pull_none>,
<1 2 RK_FUNC_1 &pcfg_pull_none>,
<1 4 RK_FUNC_1 &pcfg_pull_none>,
<1 5 RK_FUNC_1 &pcfg_pull_none>;
<1 2 RK_FUNC_2 &pcfg_pull_none>,
<1 4 RK_FUNC_2 &pcfg_pull_none>,
<1 5 RK_FUNC_2 &pcfg_pull_none>;
};
};
@@ -647,6 +1214,12 @@
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -687,9 +1260,28 @@
};
};
uart1-1 {
uart11_xfer: uart11-xfer {
rockchip,pins = <3 14 RK_FUNC_1 &pcfg_pull_up>,
<3 13 RK_FUNC_1 &pcfg_pull_none>;
};
uart11_cts: uart11-cts {
rockchip,pins = <3 7 RK_FUNC_1 &pcfg_pull_none>;
};
uart11_rts: uart11-rts {
rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_none>;
};
uart11_rts_gpio: uart11-rts-gpio {
rockchip,pins = <3 6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
<1 19 RK_FUNC_2 &pcfg_pull_none>;
};
@@ -701,5 +1293,23 @@
rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2-1 {
uart21_xfer: uart21-xfer {
rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
<1 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk322x";
status = "disabled";
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_GTCLKS
|RKPM_CTR_IDLESRAM_MD
)
>;
};
};

164
arch/arm/boot/dts/rk3288-android.dtsi
View File

@@ -41,20 +41,90 @@
*/
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include "rk3288-dram-default-timing.dtsi"
#include <dt-bindings/display/media-bus-format.h>
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff690000";
bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M";
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&efuse_id>;
nvmem-cell-names = "id";
};
/delete-node/ dmc@ff610000;
dfi: dfi {
compatible = "rockchip,rk3288-dfi";
rockchip,pmu = <&pmu>;
rockchip,grf = <&grf>;
status = "disabled";
};
dmc: dmc {
compatible = "rockchip,rk3288-dmc";
devfreq-events = <&dfi>;
clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>,
<&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>,
<&cru PCLK_DDRUPCTL1>;
clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
"pclk_phy1", "pclk_upctl1";
upthreshold = <55>;
downdifferential = <10>;
operating-points-v2 = <&dmc_opp_table>;
vop-dclk-mode = <0>;
min-cpu-freq = <600000>;
rockchip,ddr_timing = <&ddr_timing>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 396000
SYS_STATUS_REBOOT 396000
SYS_STATUS_SUSPEND 192000
SYS_STATUS_VIDEO_1080P 300000
SYS_STATUS_VIDEO_4K 396000
SYS_STATUS_PERFORMANCE 528000
SYS_STATUS_BOOST 396000
SYS_STATUS_DUALVIEW 396000
SYS_STATUS_ISP 396000
>;
auto-min-freq = <396000>;
auto-freq-en = <1>;
status = "diasbled";
};
dmc_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-microvolt = <1100000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000>;
};
opp-396000000 {
opp-hz = /bits/ 64 <396000000>;
opp-microvolt = <1100000>;
};
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <1150000>;
};
};
reserved-memory {
ramoops_mem: ramoops@00000000 {
reg = <0x8000000 0xF0000>;
reg = <0x0 0x8000000 0x0 0xF0000>;
};
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
reg = <0x0 0x0 0x0 0x0>;
};
};
@@ -69,10 +139,10 @@
fiq-debugger {
compatible = "rockchip,fiq-debugger";
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
@@ -143,13 +213,22 @@
connect = <&vopb_out_edp>;
};
route_mipi: route-mipi {
route_dsi0: route-dsi0 {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vopb_out_mipi>;
connect = <&vopb_out_dsi0>;
};
route_lvds: route-lvds {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vopb_out_lvds>;
};
};
};
@@ -209,11 +288,11 @@
dwc_control_usb: dwc-control-usb@ff770284 {
compatible = "rockchip,rk3288-dwc-control-usb";
status = "okay";
reg = <0xff770284 0x04>, <0xff770288 0x04>,
<0xff7702cc 0x04>, <0xff7702d4 0x04>,
<0xff770320 0x14>, <0xff770334 0x14>,
<0xff770348 0x10>, <0xff770358 0x08>,
<0xff770360 0x08>;
reg = <0x0 0xff770284 0x0 0x04>, <0x0 0xff770288 0x0 0x04>,
<0x0 0xff7702cc 0x0 0x04>, <0x0 0xff7702d4 0x0 0x04>,
<0x0 0xff770320 0x0 0x14>, <0x0 0xff770334 0x0 0x14>,
<0x0 0xff770348 0x0 0x10>, <0x0 0xff770358 0x0 0x08>,
<0x0 0xff770360 0x0 0x08>;
reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
"GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
"GRF_UOC0_BASE", "GRF_UOC1_BASE",
@@ -255,7 +334,25 @@
nandc_id = <0>;
clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
clock-names = "clk_nandc", "hclk_nandc";
status = "okay";
};
hdmi_analog_sound: hdmi-analog-sound {
status = "disabled";
compatible = "rockchip,rk3288-hdmi-analog",
"rockchip,rk3368-hdmi-analog";
rockchip,model = "rockchip,rt5640-codec";
rockchip,cpu = <&i2s>;
rockchip,codec = <&rt5640>, <&hdmi>;
rockchip,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
rockchip,routing =
"MIC1", "Microphone Jack",
"MIC2", "Microphone Jack",
"Microphone Jack", "micbias1",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
};
};
@@ -267,6 +364,18 @@
enable-method = "psci";
};
&cpu0_opp_table {
clocks = <&cru PLL_APLL>;
leakage-scaling-sel = <0 254 25>;
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1350000>;
clock-latency-ns = <40000>;
status = "disabled";
};
};
&cpu1 {
enable-method = "psci";
};
@@ -281,17 +390,46 @@
&dmac_bus_s {
/* change to non-secure dmac */
reg = <0xff600000 0x4000>;
reg = <0x0 0xff600000 0x0 0x4000>;
};
&efuse {
compatible = "rockchip,rk3288-secure-efuse";
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&dsi0 {
ports {
dsi0_in: port {
dsi0_in_vopl: endpoint@1 {
status = "disabled";
};
};
};
};
&edp {
ports {
edp_in: port@0 {
edp_in_vopl: endpoint@1 {
status = "disabled";
};
};
};
};
&rga {
compatible = "rockchip,rga2";
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
dma-coherent;
};
&usb_otg {

74
arch/arm/boot/dts/rk3288-dram-default-timing.dtsi Normal file
View File

@@ -0,0 +1,74 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/rk3288-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <DDR3_DEFAULT>;
pd_idle = <0x40>;
sr_idle = <0x1>;
auto_pd_dis_freq = <800>;
auto_sr_dis_freq = <800>;
ddr3_dll_dis_freq = <300>;
phy_dll_dis_freq = <250>;
ddr3_odt_dis_freq = <333>;
phy_ddr3_odt_dis_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_drv = <PHY_DDR3_RON_34ohm>;
phy_ddr3_odt = <PHY_DDR3_RTT_155ohm>;
lpddr2_drv = <LP2_DS_40ohm>;
phy_lpddr2_drv = <PHY_LP23_RON_35ohm>;
lpddr3_odt_dis_freq = <333>;
phy_lpddr3_odt_dis_freq = <333>;
lpddr3_drv = <LP3_DS_40ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_drv = <PHY_LP23_RON_35ohm>;
phy_lpddr3_odt = <PHY_LP23_RTT_155ohm>;
};
};

201
arch/arm/boot/dts/rk3288-evb-act8846.dts
View File

@@ -40,11 +40,109 @@
/dts-v1/;
#include "rk3288-evb.dtsi"
#include "rk3288-android.dtsi"
/ {
compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <1800000>;
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <100000>;
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <300000>;
};
menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <640000>;
};
esc {
label = "Esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1000000>;
};
home {
label = "Home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <1300000>;
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
button@0 {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
label = "GPIO Key Power";
linux,input-type = <1>;
gpio-key,wakeup = <1>;
debounce-interval = <100>;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
@@ -82,6 +180,11 @@
};
};
&cif_isp0 {
rockchip,camera-modules-attached = <&camera0>;
status = "disabled";
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
@@ -89,6 +192,19 @@
&edp {
vcc-supply = <&vdd10_lcd>;
vccio-supply = <&vcc18_lcd>;
status = "okay";
};
&edp_phy {
status = "okay";
};
&edp_panel {
status = "okay";
compatible ="lg,lp079qx1-sp0v", "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;
};
&gpu {
@@ -148,6 +264,7 @@
act8846: act8846@5a {
compatible = "active-semi,act8846";
reg = <0x5a>;
system-power-controller;
status = "okay";
vp1-supply = <&vcc_sys>;
@@ -246,10 +363,6 @@
};
};
&edp_panel {
power-supply = <&vcc_lcd>;
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -272,11 +385,85 @@
};
};
&lvds_panel {
power-supply = <&vcc_lcd>;
&i2c3 {
status = "okay";
camera0: camera-module@10 {
status = "disabled";
compatible = "omnivision,ov8858-v4l2-i2c-subdev";
reg = <0x10>;
device_type = "v4l2-i2c-subdev";
clocks = <&cru SCLK_VIP_OUT>;
clock-names = "clk_cif_out";
pinctrl-names = "rockchip,camera_default",
"rockchip,camera_sleep";
pinctrl-0 = <&cam0_default_pins>;
pinctrl-1 = <&cam0_sleep_pins>;
rockchip,pd-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>;
rockchip,pwr-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-mclk-name = "clk_cif_out";
rockchip,camera-module-dovdd = "1.8v";
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "cmk-cb0695-fv1";
rockchip,camera-module-len-name = "lg9569a2";
rockchip,camera-module-fov-h = "66.0";
rockchip,camera-module-fov-v = "50.1";
rockchip,camera-module-orientation = <0>;
rockchip,camera-module-iq-flip = <0>;
rockchip,camera-module-iq-mirror = <0>;
rockchip,camera-module-flip = <0>;
rockchip,camera-module-mirror = <0>;
/* resolution.w, resolution.h, defrect.left, defrect.top, defrect.w, defrect.h */
rockchip,camera-module-defrect0 = <3264 2448 0 0 3264 2448>;
rockchip,camera-module-flash-support = <0>;
rockchip,camera-module-mipi-dphy-index = <0>;
};
};
&rga {
status = "okay";
};
&sound {
status = "okay";
};
&uart2 {
status = "okay";
};
&pinctrl {
backlight {
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
cam_pins {
cam0_default_pins: cam0-default-pins {
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>,
<2 15 RK_FUNC_GPIO &pcfg_pull_none>,
<2 11 RK_FUNC_1 &pcfg_pull_none>;
};
cam0_sleep_pins: cam0-sleep-pins {
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>,
<2 15 RK_FUNC_GPIO &pcfg_pull_none>,
<2 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_en: lcd-en {
rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;

488
arch/arm/boot/dts/rk3288-evb-android-act8846-edp.dts Normal file
View File

@@ -0,0 +1,488 @@
/*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3288-evb.dtsi"
#include "rk3288-android.dtsi"
/ {
compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
};
vcc_lcd: vcc-lcd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
regulator-name = "vcc_lcd";
vin-supply = <&vcc_io>;
};
vcc_wl: vcc-wl {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pwr>;
regulator-name = "vcc_wl";
vin-supply = <&vcc_18>;
};
};
&cif_isp0 {
rockchip,camera-modules-attached = <&camera0>;
status = "disabled";
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_log>;
status = "okay";
};
&edp {
vcc-supply = <&vdd10_lcd>;
vccio-supply = <&vcc18_lcd>;
status = "okay";
};
&edp_phy {
status = "okay";
};
&edp_panel {
compatible ="lg,lp079qx1-sp0v", "simple-panel";
enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;
power-supply = <&vcc_lcd>;
delay,prepare = <120>;
status = "okay";
disp_timings: display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <200000000>;
hactive = <1536>;
vactive = <2048>;
hfront-porch = <12>;
hsync-len = <16>;
hback-porch = <48>;
vfront-porch = <8>;
vsync-len = <4>;
vback-porch = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
&gpu {
status = "okay";
mali-supply = <&vdd_gpu>;
};
&i2c0 {
clock-frequency = <400000>;
vdd_cpu: syr827@40 {
compatible = "silergy,syr827";
fcs,suspend-voltage-selector = <1>;
reg = <0x40>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <300>;
regulator-ramp-delay = <8000>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: syr828@41 {
compatible = "silergy,syr828";
fcs,suspend-voltage-selector = <1>;
reg = <0x41>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-ramp-delay = <6000>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
#clock-cells = <0>;
clock-output-names = "xin32k";
};
act8846: act8846@5a {
compatible = "active-semi,act8846";
reg = <0x5a>;
status = "okay";
vp1-supply = <&vcc_sys>;
vp2-supply = <&vcc_sys>;
vp3-supply = <&vcc_sys>;
vp4-supply = <&vcc_sys>;
inl1-supply = <&vcc_io>;
inl2-supply = <&vcc_sys>;
inl3-supply = <&vcc_20>;
regulators {
vcc_ddr: REG1 {
regulator-name = "VCC_DDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_io: REG2 {
regulator-name = "VCC_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_log: REG3 {
regulator-name = "VDD_LOG";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
};
vcc_20: REG4 {
regulator-name = "VCC_20";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-always-on;
};
vccio_sd: REG5 {
regulator-name = "VCCIO_SD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd10_lcd: REG6 {
regulator-name = "VDD10_LCD";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vcca_codec: REG7 {
regulator-name = "VCCA_CODEC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vcca_tp: REG8 {
regulator-name = "VCCA_TP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vccio_pmu: REG9 {
regulator-name = "VCCIO_PMU";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_10: REG10 {
regulator-name = "VDD_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vcc_18: REG11 {
regulator-name = "VCC_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc18_lcd: REG12 {
regulator-name = "VCC18_LCD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
mpu6050@68 {
compatible = "invensense,mpu6050";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mpu6050_irq_gpio>;
reg = <0x68>;
irq-gpio = <&gpio8 0 IRQ_TYPE_EDGE_RISING>;
mpu-int_config = <0x10>;
mpu-level_shifter = <0>;
mpu-orientation = <0 1 0 1 0 0 0 0 1>;
orientation-x= <0>;
orientation-y= <1>;
orientation-z= <0>;
support-hw-poweroff = <1>;
mpu-debug = <1>;
};
};
&i2c3 {
status = "okay";
camera0: camera-module@10 {
status = "disabled";
compatible = "omnivision,ov8858-v4l2-i2c-subdev";
reg = <0x10>;
device_type = "v4l2-i2c-subdev";
clocks = <&cru SCLK_VIP_OUT>;
clock-names = "clk_cif_out";
pinctrl-names = "rockchip,camera_default",
"rockchip,camera_sleep";
pinctrl-0 = <&cam0_default_pins>;
pinctrl-1 = <&cam0_sleep_pins>;
rockchip,pd-gpio = <&gpio2 15 GPIO_ACTIVE_LOW>;
rockchip,pwr-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-mclk-name = "clk_cif_out";
rockchip,camera-module-dovdd = "1.8v";
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "cmk-cb0695-fv1";
rockchip,camera-module-len-name = "lg9569a2";
rockchip,camera-module-fov-h = "66.0";
rockchip,camera-module-fov-v = "50.1";
rockchip,camera-module-orientation = <0>;
rockchip,camera-module-iq-flip = <0>;
rockchip,camera-module-iq-mirror = <0>;
rockchip,camera-module-flip = <0>;
rockchip,camera-module-mirror = <0>;
/* resolution.w, resolution.h, defrect.left, defrect.top, defrect.w, defrect.h */
rockchip,camera-module-defrect0 = <3264 2448 0 0 3264 2448>;
rockchip,camera-module-flash-support = <0>;
rockchip,camera-module-mipi-dphy-index = <0>;
};
};
&i2c4 {
status = "okay";
ts@01 {
compatible = "ct,vtl_ts";
reg = <0x01>;
screen_max_x = <1536>;
screen_max_y = <2048>;
xy_swap = <1>;
x_reverse = <0>;
y_reverse = <0>;
x_mul = <2>;
y_mul = <2>;
bin_ver = <0>;
irq_gpio_number = <&gpio7 6 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio7 5 GPIO_ACTIVE_HIGH>;
};
};
&lvds_panel {
power-supply = <&vcc_lcd>;
};
&rga {
status = "okay";
};
&rockchip_suspend {
status = "okay";
};
&route_edp {
status = "okay";
};
&sound {
status = "okay";
};
&uart2 {
status = "okay";
};
&pinctrl {
backlight {
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
cam_pins {
cam0_default_pins: cam0-default-pins {
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>,
<2 15 RK_FUNC_GPIO &pcfg_pull_none>,
<2 11 RK_FUNC_1 &pcfg_pull_none>;
};
cam0_sleep_pins: cam0-sleep-pins {
rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>,
<2 15 RK_FUNC_GPIO &pcfg_pull_none>,
<2 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_en: lcd-en {
rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_pwr: wifi-pwr {
rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
mpu6050 {
mpu6050_irq_gpio: mpu6050-irq-gpio {
rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

19
arch/arm/boot/dts/rk3288-evb-rk818-edp.dts → arch/arm/boot/dts/rk3288-evb-android-rk818-edp.dts
View File

@@ -45,7 +45,7 @@
#include "rk3288-android.dtsi"
/ {
compatible = "rockchip,rk3288-evb-rk818", "rockchip,rk3288";
compatible = "rockchip,rk3288-evb-android-rk818", "rockchip,rk3288";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -84,6 +84,15 @@
cpu0-supply = <&vdd_cpu>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_logic>;
status = "okay";
};
&edp {
status = "okay";
};
@@ -130,6 +139,10 @@
mali-supply = <&vdd_gpu>;
};
&hdmi_analog_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
@@ -365,6 +378,10 @@
power-supply = <&vcc_lcd>;
};
&rockchip_suspend {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */

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