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clk: rockchip: add clock controller for rk3568

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Add the clock tree definition for the new rk3568 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
This commit is contained in:
Elaine Zhang
2021-03-31 17:26:04 +08:00
committed by Tao Huang
parent 7713d7fa28
commit 849daef18c
4 changed files with 81 additions and 78 deletions
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6
drivers/clk/rockchip/Kconfig
View File

@@ -76,6 +76,12 @@ config CLK_RK3399
help
Build the driver for RK3399 Clock Driver.
config CLK_RK3568
tristate "Rockchip RK3568 clock controller support"
default y
help
Build the driver for RK3568 Clock Driver.
config ROCKCHIP_CLK_COMPENSATION
bool "Rockchip Clk Compensation"
help

1
drivers/clk/rockchip/Makefile
View File

@@ -27,3 +27,4 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o

122
drivers/clk/rockchip/clk-rk3568.c
View File

@@ -110,15 +110,6 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
#define RK3568_MUX_CLK_PVTPLL_MASK 0x1
#define RK3568_MUX_CLK_PVTPLL_SHIFT 15
#define RK3568_CLKSEL0(_apllcore, _pvtpll) \
{ \
.reg = RK3568_CLKSEL_CON(0), \
.val = HIWORD_UPDATE(_apllcore, RK3568_MUX_CLK_CORE_APLL_MASK, \
RK3568_MUX_CLK_CORE_APLL_SHIFT) | \
HIWORD_UPDATE(_pvtpll, RK3568_MUX_CLK_PVTPLL_MASK, \
RK3568_MUX_CLK_PVTPLL_SHIFT), \
}
#define RK3568_CLKSEL1(_sclk_core) \
{ \
.reg = RK3568_CLKSEL_CON(2), \
@@ -155,84 +146,64 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3568_DIV_PERIPHCLK_CORE_SHIFT), \
}
#define RK3568_CLKSEL5(_sclk_core_src) \
{ \
.reg = RK3568_CLKSEL_CON(2), \
.val = HIWORD_UPDATE(_sclk_core_src, RK3568_MUX_SCLK_CORE_MASK, \
RK3568_MUX_SCLK_CORE_SHIFT), \
}
#define RK3568_CPUCLK_RATE(_prate, _pvtpll, _apllcore, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
{ \
.prate = _prate##U, \
.divs = { \
RK3568_CLKSEL1(_sclk), \
RK3568_CLKSEL2(_acore), \
RK3568_CLKSEL3(_atcore, _gicclk), \
RK3568_CLKSEL4(_pclk, _periph), \
}, \
.pre_muxs = { \
RK3568_CLKSEL0(0, _pvtpll), \
RK3568_CLKSEL5(1), \
}, \
.post_muxs = { \
RK3568_CLKSEL0(_apllcore, _pvtpll), \
RK3568_CLKSEL1(_sclk), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
RK3568_CPUCLK_RATE(2208000000, 1, 1, 1, 1, 9, 9, 9, 9),
RK3568_CPUCLK_RATE(2184000000, 1, 1, 1, 1, 9, 9, 9, 9),
RK3568_CPUCLK_RATE(2088000000, 1, 1, 1, 1, 9, 9, 9, 9),
RK3568_CPUCLK_RATE(2040000000, 1, 1, 1, 1, 9, 9, 9, 9),
RK3568_CPUCLK_RATE(2016000000, 1, 1, 1, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1992000000, 1, 1, 1, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1896000000, 1, 1, 1, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1800000000, 1, 1, 1, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1704000000, 0, 1, 1, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1608000000, 0, 1, 1, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1584000000, 0, 1, 1, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1560000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1536000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1512000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1488000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1464000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1440000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1416000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1392000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1368000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1344000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1320000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1296000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1272000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1248000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1224000000, 0, 0, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1200000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1104000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1008000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(912000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(816000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(696000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(600000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(408000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(312000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(216000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(96000000, 0, 0, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
};
static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
.core_reg = RK3568_CLKSEL_CON(0),
.div_core_shift = 0,
.div_core_mask = 0x1f,
.core1_reg = RK3568_CLKSEL_CON(0),
.div_core1_shift = 8,
.div_core1_mask = 0x1f,
.core2_reg = RK3568_CLKSEL_CON(1),
.div_core2_shift = 0,
.div_core2_mask = 0x1f,
.core3_reg = RK3568_CLKSEL_CON(1),
.div_core3_shift = 8,
.div_core3_mask = 0x1f,
.core_reg[0] = RK3568_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.core_reg[1] = RK3568_CLKSEL_CON(0),
.div_core_shift[1] = 8,
.div_core_mask[1] = 0x1f,
.core_reg[2] = RK3568_CLKSEL_CON(1),
.div_core_shift[2] = 0,
.div_core_mask[2] = 0x1f,
.core_reg[3] = RK3568_CLKSEL_CON(1),
.div_core_shift[3] = 8,
.div_core_mask[3] = 0x1f,
.num_cores = 4,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 6,
@@ -620,9 +591,6 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKGATE_CON(3), 12, GFLAGS),
/* PD_DDR */
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", dpll_gpll_cpll_p,
CLK_IGNORE_UNUSED, RK3568_CLKSEL_CON(9), 6, 2, 0, 5,
ROCKCHIP_DDRCLK_SIP_V2),
COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(4), 0, GFLAGS),

30
drivers/clk/rockchip/clk.h
View File

@@ -201,6 +201,34 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4
#define RK3568_MISC_CON1 0xc8
#define RK3568_MISC_CON2 0xcc
#define RK3568_GLB_CNT_TH 0xd0
#define RK3568_GLB_SRST_FST 0xd4
#define RK3568_GLB_SRST_SND 0xd8
#define RK3568_GLB_RST_CON 0xdc
#define RK3568_GLB_RST_ST 0xe0
#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
#define RK3568_SDMMC0_CON0 0x580
#define RK3568_SDMMC0_CON1 0x584
#define RK3568_SDMMC1_CON0 0x588
#define RK3568_SDMMC1_CON1 0x58c
#define RK3568_SDMMC2_CON0 0x590
#define RK3568_SDMMC2_CON1 0x594
#define RK3568_EMMC_CON0 0x598
#define RK3568_EMMC_CON1 0x59c
#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_PMU_MODE_CON0 0x80
#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
@@ -344,7 +372,7 @@ struct rockchip_cpuclk_clksel {
u32 val;
};
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5
#define ROCKCHIP_CPUCLK_MAX_CORES 4
struct rockchip_cpuclk_rate_table {
unsigned long prate;