arm64: dts: rockchip: rk3328: add vpu_combo and enable it

add vpu_combo consist of avsd and vdpu

Change-Id: Ib49238d6a187dd7d621ad40ee0635b74825931f8
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
This commit is contained in:
Xinhuang Li
2018-01-08 17:59:32 +08:00
committed by Tao Huang
parent 68369a5869
commit 85404c0b12

View File

@@ -640,19 +640,17 @@
compatible = "rockchip,mpp_service";
};
vpu_service: vpu-service@ff350000 {
compatible = "rockchip,vpu_service";
vdpu: vpu_service@ff350000 {
compatible = "vpu,sub";
iommu_enabled = <1>;
iommus = <&vpu_mmu>;
allocator = <1>;
reg = <0x0 0xff350000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
reset-names = "video_a", "video_h";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,grf = <&grf>;
iommus = <&vpu_mmu>;
allocator = <1>;
status = "disabled";
dev_mode = <0>;
power-domains = <&power RK3328_PD_VPU>;
name = "vpu_service";
};
vpu_mmu: iommu@ff350800 {
@@ -662,9 +660,39 @@
interrupt-names = "vpu_mmu";
clock-names = "aclk", "hclk";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3328_PD_VPU>;
#iommu-cells = <0>;
};
avsd: avsd@ff351000 {
compatible = "vpu,sub";
iommu_enabled = <1>;
iommus = <&vpu_mmu>;
allocator = <1>;
reg = <0x0 0xff351000 0x0 0x200>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
power-domains = <&power RK3328_PD_VPU>;
dev_mode = <0>;
name = "avsd";
};
vpu_service: vpu_combo {
compatible = "rockchip,rk3328-vpu-combo", "rockchip,vpu_combo";
rockchip,grf = <&grf>;
subcnt = <2>;
rockchip,sub = <&vdpu>, <&avsd>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
reset-names = "video_a", "video_h";
mode_bit = <0>;
mode_ctrl = <0>;
name = "vpu_combo";
power-domains = <&power RK3328_PD_VPU>;
status = "disabled";
};
rkvdec: rkvdec@ff36000 {
compatible = "rockchip,rkvdec";
reg = <0x0 0xff360000 0x0 0x400>;