video: rockchip: rga3: open RGA2 optimization options

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com> Change-Id: I6597b9e5b026e609a93d61bed08368ef378fd3d8
2026-06-06 19:08:57 +09:00 · 2025-03-24 16:59:44 +08:00
parent 807eca48f7
commit 85edaf5c3d
3 changed files with 68 additions and 14 deletions
--- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h
+++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h
@@ -6,6 +6,7 @@

 #define RGA2_SYS_REG_BASE			0x000
 #define RGA2_CSC_REG_BASE			0x060
+#define RGA2_OTHER_REG_BASE			0x090
 #define RGA2_CMD_REG_BASE			0x100

 /* sys reg */
@@ -38,9 +39,14 @@
 #define RGA2_DST_CSC_22				0x088
 #define RGA2_DST_CSC_OFF2			0x08c

+/* back door0 */
+#define RGA2_BACKDOOR0				0x090
+
 /* osd read-back reg */
 #define RGA2_OSD_CUR_FLAGS0			0x090
 #define RGA2_OSD_CUR_FLAGS1			0x09c
+#define RGA2_FIXED_OSD_CUR_FLAGS0		0x440
+#define RGA2_FIXED_OSD_CUR_FLAGS1		0x444

 /* mode ctrl */
 #define RGA2_MODE_CTRL_OFFSET			0x000
@@ -94,6 +100,7 @@
 #define RGA2_OSD_INVERTSION_CAL1_OFFSET		0x064 // repeat
 #define RGA2_MASK_BASE_OFFSET			0x068
 #define RGA2_MMU_CTRL1_OFFSET			0x06c
+#define RGA2_UV_VIR_INFO			0x06c // repeat
 #define RGA2_MMU_SRC_BASE_OFFSET		0x070
 #define RGA2_PREFETCH_ADDR_TH_OFFSET		0x070 // repeat
 #define RGA2_MMU_SRC1_BASE_OFFSET		0x074
@@ -101,8 +108,9 @@
 #define RGA2_MMU_ELS_BASE_OFFSET		0x07c

 /*RGA_SYS*/
-#define m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS		(0x1 << 12)
-#define m_RGA2_SYS_CTRL_DST_WR_OPT_DIS			(0x1 << 11)
+#define m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS		(0x1 << 12) /* moved to RGA_BACKDOOR0 since RV1126B */
+#define m_RGA2_SYS_CTRL_DST_WR_OPT_DIS			(0x1 << 11) /* moved to RGA_BACKDOOR0 since RV1126B */
+#define m_RGA2_MASTER_CMD_BYPASS_EN			(0x1 << 11) /* after RV1126B */
 #define m_RGA2_SYS_CTRL_CMD_CONTINUE_P			(0x1 << 10)
 #define m_RGA2_SYS_CTRL_HOLD_MODE_EN			(0x1 << 9)
 #define m_RGA2_SYS_CTRL_RST_HANDSAVE_P			(0x1 << 7)
@@ -211,6 +219,17 @@
 #define s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_START(x)	((x & 0x1fff) << 0)
 #define s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP(x)	((x & 0x1fff) << 16)

+/* RGA BACKDOOR0 */
+#define m_RGA2_HSDBIL_VSP_FIX_DIS			(0x1 << 0)
+#define m_RGA2_HSP_LEFT_COPY_DIS			(0x1 << 1)
+#define m_RGA2_AXI_WR128_DIS				(0x1 << 2)
+#define m_RGA2_TABLE_PRE_FETCH_DIS			(0X1 << 3)
+#define m_RGA2_FBCIN_BSP_DIS				(0X1 << 4)
+#define m_RGA2_SRC1_RGB888_FIX_DIS			(0X1 << 5)
+#define m_RGA2_SRC0_YUV420SP_RD_OPT_DIS			(0X1 << 6)
+#define m_RGA2_DST_WR_OPT_DIS				(0X1 << 7)
+#define m_RGA2_OUTSTANDING_CFG_DIS			(0X1 << 8)
+
 /* RGA_MODE_CTRL */
 #define m_RGA2_MODE_CTRL_SW_RENDER_MODE			(0x7 << 0)
 #define m_RGA2_MODE_CTRL_SW_BITBLT_MODE			(0x1 << 3)
@@ -225,10 +244,10 @@
 #define m_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN		(0x1 << 13)
 #define m_RGA2_MODE_CTRL_SW_FBC_IN_EN			(0x1 << 16)
 #define m_RGA2_MODE_CTRL_SW_SRC_GAUSS_EN		(0x1 << 17)
-#define m_RGA2_MODE_CTRL_SW_FBC_BSP_DIS			(0x1 << 18)
-#define m_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_DIS		(0x1 << 19)
-#define m_RGA2_MODE_CTRL_SW_AXI_WR128_DIS		(0x1 << 20)
-#define m_RGA2_MODE_CTRL_SW_HSP_LEFT_COPY_DIS		(0x1 << 21)
+#define m_RGA2_MODE_CTRL_SW_FBC_BSP_DIS			(0x1 << 18) /* moved to RGA_BACKDOOR0 since RV1126B */
+#define m_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_DIS		(0x1 << 19) /* moved to RGA_BACKDOOR0 since RV1126B */
+#define m_RGA2_MODE_CTRL_SW_AXI_WR128_DIS		(0x1 << 20) /* moved to RGA_BACKDOOR0 since RV1126B */
+#define m_RGA2_MODE_CTRL_SW_HSP_LEFT_COPY_DIS		(0x1 << 21) /* moved to RGA_BACKDOOR0 since RV1126B */

 #define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x)		((x & 0x7) << 0)
 #define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x)		((x & 0x1) << 3)
--- a/drivers/video/rockchip/rga3/rga2_reg_info.c
+++ b/drivers/video/rockchip/rga3/rga2_reg_info.c
@@ -2958,6 +2958,27 @@ static void rga2_dump_read_back_csc_reg(struct rga_job *job, struct rga_schedule
 			csc_reg[2 + i * 4], csc_reg[3 + i * 4]);
 }

+static void rga2_dump_read_back_other_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
+{
+	int i;
+	unsigned long flags;
+	uint32_t other_reg[4] = {0};
+
+	spin_lock_irqsave(&scheduler->irq_lock, flags);
+
+	for (i = 0; i < 4; i++)
+		other_reg[i] = rga_read(RGA2_OTHER_REG_BASE + i * 4, scheduler);
+
+	spin_unlock_irqrestore(&scheduler->irq_lock, flags);
+
+	rga_job_log(job, "OTHER_READ_BACK_REG\n");
+	for (i = 0; i < 1; i++)
+		rga_job_log(job, "0x%04x : %.8x %.8x %.8x %.8x\n",
+			RGA2_OTHER_REG_BASE + i * 0x10,
+			other_reg[0 + i * 4], other_reg[1 + i * 4],
+			other_reg[2 + i * 4], other_reg[3 + i * 4]);
+}
+
 static void rga2_dump_read_back_cmd_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 {
 	int i;
@@ -2983,6 +3004,8 @@ static void rga2_dump_read_back_reg(struct rga_job *job, struct rga_scheduler_t
 {
 	rga2_dump_read_back_sys_reg(job, scheduler);
 	rga2_dump_read_back_csc_reg(job, scheduler);
+	if (scheduler->data->version > 0)
+		rga2_dump_read_back_other_reg(job, scheduler);
 	rga2_dump_read_back_cmd_reg(job, scheduler);
 }

@@ -3065,6 +3088,8 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 	if (DEBUGGER_EN(REG)) {
 		rga2_dump_read_back_sys_reg(job, scheduler);
 		rga2_dump_read_back_csc_reg(job, scheduler);
+		if (scheduler->data->version > 0)
+			rga2_dump_read_back_other_reg(job, scheduler);

 		rga_job_log(job, "CMD_REG\n");
 		for (i = 0; i < 8; i++)
@@ -3077,9 +3102,11 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 	spin_lock_irqsave(&scheduler->irq_lock, flags);

 	/* sys_reg init */
-	sys_ctrl = m_RGA2_SYS_CTRL_AUTO_CKG |
-		   m_RGA2_SYS_CTRL_DST_WR_OPT_DIS |
-		   m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS;
+	sys_ctrl = m_RGA2_SYS_CTRL_AUTO_CKG;
+
+	/* RV1106 need disables these optimizations */
+	if (scheduler->data == &rga2e_1106_data)
+		sys_ctrl |= m_RGA2_SYS_CTRL_DST_WR_OPT_DIS | m_RGA2_SRC0_YUV420SP_RD_OPT_DIS;

 	if (rga_hw_has_issue(scheduler, RGA_HW_ISSUE_DIS_AUTO_RST)) {
 		/*
@@ -3174,10 +3201,17 @@ static int rga2_get_version(struct rga_scheduler_t *scheduler)
 static int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 {
 	if (job->rga_command_base.osd_info.enable) {
-		job->rga_command_base.osd_info.cur_flags0 = rga_read(RGA2_OSD_CUR_FLAGS0,
-								     scheduler);
-		job->rga_command_base.osd_info.cur_flags1 = rga_read(RGA2_OSD_CUR_FLAGS1,
-								     scheduler);
+		if (scheduler->data->version == 0) {
+			job->rga_command_base.osd_info.cur_flags0 =
+				rga_read(RGA2_OSD_CUR_FLAGS0, scheduler);
+			job->rga_command_base.osd_info.cur_flags1 =
+				rga_read(RGA2_OSD_CUR_FLAGS1, scheduler);
+		} else {
+			job->rga_command_base.osd_info.cur_flags0 =
+				rga_read(RGA2_FIXED_OSD_CUR_FLAGS0, scheduler);
+			job->rga_command_base.osd_info.cur_flags1 =
+				rga_read(RGA2_FIXED_OSD_CUR_FLAGS1, scheduler);
+		}
 	}

 	return 0;
--- a/drivers/video/rockchip/rga3/rga_hw_config.c
+++ b/drivers/video/rockchip/rga3/rga_hw_config.c
@@ -710,7 +710,8 @@ const struct rga_hw_data rga2p_lite_1103b_data = {
 };

 const struct rga_hw_data rga2p_iommu_non_fbc_data = {
-	.version = 0,
+	/* Register have changed, so the version is increased. */
+	.version = 1,
 	.input_range = {{2, 2}, {8192, 8192}},
 	.output_range = {{2, 2}, {8192, 8192}},