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Merge commit 'fa133f475e84216d901eedbe6350a22bcf7c0ea0'

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* commit 'fa133f475e84216d901eedbe6350a22bcf7c0ea0':
  media: rockchip: isp: fix build error for kernel 6.1
  media: rockchip: ispp: fix build error for kernel 6.1
  media: rockchip: isp1: fix build error for kernel 6.1
  arm64: dts: rockchip: rk3588s: Add trips for some thermal nodes
  phy: rockchip: csi2-dphy: do not to check port when parse fwnode
  media: rockchip: vicap: fixes build error
  media: i2c: fixes sensor driver for kernel-6.1

Change-Id: Ic0aa75bcc23686dca78aea7e16bb2e17e207c637
This commit is contained in:
Tao Huang
2023-06-08 15:27:42 +08:00
parent 2db8874b52 fa133f475e
commit 8609a572ae
148 changed files with 1057 additions and 1965 deletions
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54
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -1772,36 +1772,90 @@
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
trips {
bigcore0_crit: bigcore0-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
bigcore1_thermal: bigcore1-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 2>;
trips {
bigcore1_crit: bigcore1-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
little_core_thermal: littlecore-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 3>;
trips {
litcore_crit: litcore-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
center_thermal: center-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 4>;
trips {
center_crit: center-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 5>;
trips {
gpu_crit: gpu-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
npu_thermal: npu-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 6>;
trips {
npu_crit: npu-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
};

153
drivers/media/i2c/Kconfig
View File

@@ -60,6 +60,19 @@ config VIDEO_AR0521
To compile this driver as a module, choose M here: the
module will be called ar0521.
config VIDEO_BF3925
tristate "BYD BF3925 sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the BYD
BF3925 camera.
To compile this driver as a module, choose M here: the
module will be called BF3925.
config VIDEO_GC02M2
tristate "GalaxyCore GC02M2 sensor support"
depends on I2C && VIDEO_DEV
@@ -73,6 +86,45 @@ config VIDEO_GC02M2
To compile this driver as a module, choose M here: the
module will be called gc02m2.
config VIDEO_GC0312
tristate "GalaxyCore GC0312 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC0312 sensor.
To compile this driver as a module, choose M here: the
module will be called GC0312.
config VIDEO_GC0329
tristate "GalaxyCore GC0329 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC0329 sensor.
To compile this driver as a module, choose M here: the
module will be called GC0329.
config VIDEO_GC0403
tristate "GalaxyCore GC0403 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC0403 sensor.
To compile this driver as a module, choose M here: the
module will be called GC0403.
config VIDEO_GC08A3
tristate "GalaxyCore GC08A3 sensor support"
depends on I2C && VIDEO_DEV
@@ -99,6 +151,19 @@ config VIDEO_GC1084
To compile this driver as a module, choose M here: the
module will be called gc1084.
config VIDEO_GC2035
tristate "GalaxyCore GC2035 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC2035 sensor.
To compile this driver as a module, choose M here: the
module will be called GC2035.
config VIDEO_GC2053
tristate "GalaxyCore GC2053 sensor support"
depends on I2C && VIDEO_DEV
@@ -138,6 +203,45 @@ config VIDEO_GC2145
To compile this driver as a module, choose M here: the
module will be called gc2145.
config VIDEO_GC2155
tristate "GalaxyCore GC2155 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC2155 sensor.
To compile this driver as a module, choose M here: the
module will be called GC2155.
config VIDEO_GC2355
tristate "GalaxyCore GC2355 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC2355 sensor.
To compile this driver as a module, choose M here: the
module will be called GC2355.
config VIDEO_GC2375H
tristate "GalaxyCore GC2375H sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC2375H sensor.
To compile this driver as a module, choose M here: the
module will be called GC2375H.
config VIDEO_GC2385
tristate "GalaxyCore GC2385 sensor support"
depends on I2C && VIDEO_DEV
@@ -216,6 +320,19 @@ config VIDEO_GC4C33
To compile this driver as a module, choose M here: the
module will be called gc4C33.
config VIDEO_GC5024
tristate "GalaxyCore GC5024 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
Support for the GalaxyCore GC5024 sensor.
To compile this driver as a module, choose M here: the
module will be called gc5024.
config VIDEO_GC5025
tristate "GalaxyCore GC5025 sensor support"
depends on I2C && VIDEO_DEV
@@ -595,6 +712,42 @@ config VIDEO_IMX586
To compile this driver as a module, choose M here: the
module will be called imx586.
config VIDEO_JX_F37
tristate "Soi JX_F37 sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
help
This is a Video4Linux2 sensor driver for the Soi
JX_F37 camera.
To compile this driver as a module, choose M here: the
module will be called jx_f37.
config VIDEO_JX_H62
tristate "Soi JX_H62 sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
help
This is a Video4Linux2 sensor driver for the Soi
JX_H62 camera.
To compile this driver as a module, choose M here: the
module will be called jx_h62.
config VIDEO_JX_H65
tristate "Soi JX_H65 sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
help
This is a Video4Linux2 sensor driver for the Soi
JX_H65 camera.
To compile this driver as a module, choose M here: the
module will be called jx_h65.
config VIDEO_JX_K17
tristate "Soi JX_K17 sensor support"
depends on I2C && VIDEO_DEV

12
drivers/media/i2c/Makefile
View File

@@ -23,6 +23,7 @@ obj-$(CONFIG_VIDEO_AR0230) += ar0230.o
obj-$(CONFIG_VIDEO_AR0521) += ar0521.o
obj-$(CONFIG_VIDEO_AW36518) += aw36518.o
obj-$(CONFIG_VIDEO_AW8601) += aw8601.o
obj-$(CONFIG_VIDEO_BF3925) += bf3925.o
obj-$(CONFIG_VIDEO_BT819) += bt819.o
obj-$(CONFIG_VIDEO_BT856) += bt856.o
obj-$(CONFIG_VIDEO_BT866) += bt866.o
@@ -42,17 +43,25 @@ obj-$(CONFIG_VIDEO_EP9461E) += ep9461e.o
obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
obj-$(CONFIG_VIDEO_FP5510) += fp5510.o
obj-$(CONFIG_VIDEO_GC02M2) += gc02m2.o
obj-$(CONFIG_VIDEO_GC0312) += gc0312.o
obj-$(CONFIG_VIDEO_GC0329) += gc0329.o
obj-$(CONFIG_VIDEO_GC0403) += gc0403.o
obj-$(CONFIG_VIDEO_GC08A3) += gc08a3.o
obj-$(CONFIG_VIDEO_GC1084) += gc1084.o
obj-$(CONFIG_VIDEO_GC2035) += gc2035.o
obj-$(CONFIG_VIDEO_GC2053) += gc2053.o
obj-$(CONFIG_VIDEO_GC2093) += gc2093.o
obj-$(CONFIG_VIDEO_GC2145) += gc2145.o
obj-$(CONFIG_VIDEO_GC2155) += gc2155.o
obj-$(CONFIG_VIDEO_GC2355) += gc2355.o
obj-$(CONFIG_VIDEO_GC2375H) += gc2375h.o
obj-$(CONFIG_VIDEO_GC2385) += gc2385.o
obj-$(CONFIG_VIDEO_GC3003) += gc3003.o
obj-$(CONFIG_VIDEO_GC4023) += gc4023.o
obj-$(CONFIG_VIDEO_GC4653) += gc4653.o
obj-$(CONFIG_VIDEO_GC4663) += gc4663.o
obj-$(CONFIG_VIDEO_GC4C33) += gc4c33.o
obj-$(CONFIG_VIDEO_GC5024) += gc5024.o
obj-$(CONFIG_VIDEO_GC5025) += gc5025.o
obj-$(CONFIG_VIDEO_GC5035) += gc5035.o
obj-$(CONFIG_VIDEO_GC8034) += gc8034.o
@@ -88,6 +97,9 @@ obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o
obj-$(CONFIG_VIDEO_IT6616) += it6616.o
obj-$(CONFIG_VIDEO_IT66353) += it66353/
obj-$(CONFIG_VIDEO_JX_F37) += jx_f37.o
obj-$(CONFIG_VIDEO_JX_H62) += jx_h62.o
obj-$(CONFIG_VIDEO_JX_H65) += jx_h65.o
obj-$(CONFIG_VIDEO_JX_K17) += jx_k17.o
obj-$(CONFIG_VIDEO_KS0127) += ks0127.o
obj-$(CONFIG_VIDEO_LM3560) += lm3560.o

2
drivers/media/i2c/ar0230.c
View File

@@ -1294,7 +1294,7 @@ static int ar0230_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_HIGH |
V4L2_MBUS_PCLK_SAMPLE_FALLING;
return 0;

6
drivers/media/i2c/bf3925.c
View File

@@ -967,11 +967,11 @@ static int bf3925_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
}
#endif
static int bf3925_g_mbus_config(struct v4l2_subdev *sd,
static int bf3925_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_LOW |
V4L2_MBUS_PCLK_SAMPLE_RISING;
@@ -1180,7 +1180,6 @@ static const struct v4l2_subdev_core_ops bf3925_subdev_core_ops = {
static const struct v4l2_subdev_video_ops bf3925_subdev_video_ops = {
.s_stream = bf3925_s_stream,
.g_mbus_config = bf3925_g_mbus_config,
.g_frame_interval = bf3925_g_frame_interval,
.s_frame_interval = bf3925_s_frame_interval,
};
@@ -1191,6 +1190,7 @@ static const struct v4l2_subdev_pad_ops bf3925_subdev_pad_ops = {
.enum_frame_interval = bf3925_enum_frame_interval,
.get_fmt = bf3925_get_fmt,
.set_fmt = bf3925_set_fmt,
.get_mbus_config = bf3925_g_mbus_config,
};
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API

13
drivers/media/i2c/gc02m2.c
View File

@@ -374,7 +374,7 @@ static const struct gc02m2_mode supported_modes[] = {
.vts_def = 0x04f4,
.reg_list = gc02m2_global_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -971,17 +971,8 @@ static int gc02m2_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
static int gc02m2_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc02m2 *gc02m2 = to_gc02m2(sd);
const struct gc02m2_mode *mode = gc02m2->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (GC02M2_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC02M2_LANES;
return 0;
}

6
drivers/media/i2c/gc0312.c
View File

@@ -909,11 +909,11 @@ static int gc0312_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
}
#endif
static int gc0312_g_mbus_config(struct v4l2_subdev *sd,
static int gc0312_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_LOW |
V4L2_MBUS_PCLK_SAMPLE_RISING;
@@ -946,7 +946,6 @@ static const struct v4l2_subdev_core_ops gc0312_subdev_core_ops = {
static const struct v4l2_subdev_video_ops gc0312_subdev_video_ops = {
.s_stream = gc0312_s_stream,
.g_mbus_config = gc0312_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops gc0312_subdev_pad_ops = {
@@ -955,6 +954,7 @@ static const struct v4l2_subdev_pad_ops gc0312_subdev_pad_ops = {
.enum_frame_interval = gc0312_enum_frame_interval,
.get_fmt = gc0312_get_fmt,
.set_fmt = gc0312_set_fmt,
.get_mbus_config = gc0312_g_mbus_config,
};
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API

6
drivers/media/i2c/gc0329.c
View File

@@ -842,11 +842,11 @@ static int gc0329_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
}
#endif
static int gc0329_g_mbus_config(struct v4l2_subdev *sd,
static int gc0329_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_HIGH |
V4L2_MBUS_PCLK_SAMPLE_RISING;
@@ -920,7 +920,6 @@ static const struct v4l2_subdev_core_ops gc0329_subdev_core_ops = {
static const struct v4l2_subdev_video_ops gc0329_subdev_video_ops = {
.s_stream = gc0329_s_stream,
.g_mbus_config = gc0329_g_mbus_config,
.g_frame_interval = gc0329_g_frame_interval,
.s_frame_interval = gc0329_s_frame_interval,
};
@@ -931,6 +930,7 @@ static const struct v4l2_subdev_pad_ops gc0329_subdev_pad_ops = {
.enum_frame_interval = gc0329_enum_frame_interval,
.get_fmt = gc0329_get_fmt,
.set_fmt = gc0329_set_fmt,
.get_mbus_config = gc0329_g_mbus_config,
};
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API

6
drivers/media/i2c/gc032a.c
View File

@@ -900,11 +900,11 @@ static int gc032a_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
}
#endif
static int gc032a_g_mbus_config(struct v4l2_subdev *sd,
static int gc032a_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_LOW |
V4L2_MBUS_PCLK_SAMPLE_RISING;
@@ -964,7 +964,6 @@ static const struct v4l2_subdev_core_ops gc032a_subdev_core_ops = {
static const struct v4l2_subdev_video_ops gc032a_subdev_video_ops = {
.s_stream = gc032a_s_stream,
.g_mbus_config = gc032a_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops gc032a_subdev_pad_ops = {
@@ -973,6 +972,7 @@ static const struct v4l2_subdev_pad_ops gc032a_subdev_pad_ops = {
.enum_frame_interval = gc032a_enum_frame_interval,
.get_fmt = gc032a_get_fmt,
.set_fmt = gc032a_set_fmt,
.get_mbus_config = gc032a_g_mbus_config,
};
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API

13
drivers/media/i2c/gc0403.c
View File

@@ -913,16 +913,11 @@ static int gc0403_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int gc0403_g_mbus_config(struct v4l2_subdev *sd,
static int gc0403_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (GC0403_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = GC0403_LANES;
return 0;
}
@@ -949,7 +944,6 @@ static struct v4l2_subdev_core_ops gc0403_core_ops = {
static const struct v4l2_subdev_video_ops gc0403_video_ops = {
.s_stream = gc0403_s_stream,
.g_frame_interval = gc0403_g_frame_interval,
.g_mbus_config = gc0403_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops gc0403_pad_ops = {
@@ -958,6 +952,7 @@ static const struct v4l2_subdev_pad_ops gc0403_pad_ops = {
.enum_frame_interval = gc0403_enum_frame_interval,
.get_fmt = gc0403_get_fmt,
.set_fmt = gc0403_set_fmt,
.get_mbus_config = gc0403_g_mbus_config,
};
static const struct v4l2_subdev_ops gc0403_subdev_ops = {

17
drivers/media/i2c/gc08a3.c
View File

@@ -1061,7 +1061,7 @@ static const struct gc08a3_mode supported_modes_4lane[] = {
.reg_list = gc08a3_3264x2448_regs_4lane,
.global_reg_list = gc08a3_global_regs_4lane,
.mipi_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 1280,
@@ -1076,7 +1076,7 @@ static const struct gc08a3_mode supported_modes_4lane[] = {
.reg_list = gc08a3_1280x800_regs_4lane,
.global_reg_list = gc08a3_global_regs_4lane,
.mipi_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 1280,
@@ -1091,7 +1091,7 @@ static const struct gc08a3_mode supported_modes_4lane[] = {
.reg_list = gc08a3_1280x720_regs_4lane,
.global_reg_list = gc08a3_global_regs_4lane,
.mipi_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1713,16 +1713,9 @@ static int gc08a3_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
if (2 == sensor->lane_num) {
if (2 == sensor->lane_num || 4 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2.num_data_lanes = sensor->lane_num;
} else {
dev_err(&sensor->client->dev,
"unsupported lane_num(%d)\n", sensor->lane_num);

9
drivers/media/i2c/gc1084.c
View File

@@ -289,7 +289,7 @@ static const struct gc1084_mode supported_modes[] = {
.reg_list = gc1084_1280x720_liner_settings,
.reg_num = ARRAY_SIZE(gc1084_1280x720_liner_settings),
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -847,13 +847,8 @@ static int gc1084_g_frame_interval(struct v4l2_subdev *sd,
static int gc1084_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc1084 *gc1084 = to_gc1084(sd);
u32 val = 1 << (GC1084_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = (gc1084->cur_mode->hdr_mode == NO_HDR) ?
val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
config->bus.mipi_csi2.num_data_lanes = GC1084_LANES;
return 0;
}

6
drivers/media/i2c/gc2035.c
View File

@@ -1150,11 +1150,11 @@ static int gc2035_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
}
#endif
static int gc2035_g_mbus_config(struct v4l2_subdev *sd,
static int gc2035_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_HIGH |
V4L2_MBUS_PCLK_SAMPLE_RISING;
@@ -1311,7 +1311,6 @@ static const struct v4l2_subdev_core_ops gc2035_subdev_core_ops = {
static const struct v4l2_subdev_video_ops gc2035_subdev_video_ops = {
.s_stream = gc2035_s_stream,
.g_mbus_config = gc2035_g_mbus_config,
.g_frame_interval = gc2035_g_frame_interval,
.s_frame_interval = gc2035_s_frame_interval,
};
@@ -1322,6 +1321,7 @@ static const struct v4l2_subdev_pad_ops gc2035_subdev_pad_ops = {
.enum_frame_interval = gc2035_enum_frame_interval,
.get_fmt = gc2035_get_fmt,
.set_fmt = gc2035_set_fmt,
.get_mbus_config = gc2035_g_mbus_config,
};
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API

14
drivers/media/i2c/gc2053.c
View File

@@ -336,7 +336,7 @@ static const struct gc2053_mode supported_modes[] = {
.vts_def = 0x465,
.reg_list = gc2053_1920x1080_regs_2lane,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1141,19 +1141,11 @@ static int gc2053_g_frame_interval(struct v4l2_subdev *sd,
static int gc2053_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc2053 *gc2053 = to_gc2053(sd);
const struct gc2053_mode *mode = gc2053->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (GC2053_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC2053_LANES;
return 0;
}
static int gc2053_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)

17
drivers/media/i2c/gc2093.c
View File

@@ -436,7 +436,7 @@ static const struct gc2093_mode supported_modes[] = {
.reg_list = gc2093_1080p_liner_settings,
.reg_num = ARRAY_SIZE(gc2093_1080p_liner_settings),
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 1920,
@@ -452,10 +452,10 @@ static const struct gc2093_mode supported_modes[] = {
.reg_list = gc2093_1080p_hdr_settings,
.reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1159,13 +1159,8 @@ static int gc2093_g_frame_interval(struct v4l2_subdev *sd,
static int gc2093_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc2093 *gc2093 = to_gc2093(sd);
u32 val = 1 << (GC2093_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = (gc2093->cur_mode->hdr_mode == NO_HDR) ?
val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
config->bus.mipi_csi2.num_data_lanes = GC2093_LANES;
return 0;
}

8
drivers/media/i2c/gc2145.c
View File

@@ -2465,14 +2465,10 @@ static int gc2145_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
if (gc2145->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_1_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2 = gc2145->bus_cfg.bus.mipi_csi2;
} else {
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_LOW |
V4L2_MBUS_PCLK_SAMPLE_RISING;
config->bus.parallel = gc2145->bus_cfg.bus.parallel;
}
return 0;

6
drivers/media/i2c/gc2155.c
View File

@@ -1383,11 +1383,11 @@ static int gc2155_runtime_suspend(struct device *dev)
return 0;
}
static int gc2155_g_mbus_config(struct v4l2_subdev *sd,
static int gc2155_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_LOW |
V4L2_MBUS_PCLK_SAMPLE_RISING;
@@ -1510,7 +1510,6 @@ static const struct v4l2_subdev_core_ops gc2155_core_ops = {
static const struct v4l2_subdev_video_ops gc2155_video_ops = {
.s_stream = gc2155_s_stream,
.g_mbus_config = gc2155_g_mbus_config,
.g_frame_interval = gc2155_g_frame_interval,
.s_frame_interval = gc2155_s_frame_interval,
};
@@ -1521,6 +1520,7 @@ static const struct v4l2_subdev_pad_ops gc2155_pad_ops = {
.enum_frame_interval = gc2155_enum_frame_interval,
.get_fmt = gc2155_get_fmt,
.set_fmt = gc2155_set_fmt,
.get_mbus_config = gc2155_g_mbus_config,
};
static const struct v4l2_subdev_ops gc2155_subdev_ops = {

12
drivers/media/i2c/gc2355.c
View File

@@ -822,16 +822,12 @@ static int gc2355_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int gc2355_g_mbus_config(struct v4l2_subdev *sd,
static int gc2355_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (GC2355_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = GC2355_LANES;
return 0;
}
@@ -857,7 +853,6 @@ static const struct v4l2_subdev_core_ops gc2355_core_ops = {
static const struct v4l2_subdev_video_ops gc2355_video_ops = {
.s_stream = gc2355_s_stream,
.g_frame_interval = gc2355_g_frame_interval,
.g_mbus_config = gc2355_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops gc2355_pad_ops = {
@@ -866,6 +861,7 @@ static const struct v4l2_subdev_pad_ops gc2355_pad_ops = {
.enum_frame_interval = gc2355_enum_frame_interval,
.get_fmt = gc2355_get_fmt,
.set_fmt = gc2355_set_fmt,
.get_mbus_config = gc2355_g_mbus_config,
};
static const struct v4l2_subdev_ops gc2355_subdev_ops = {

13
drivers/media/i2c/gc2375h.c
View File

@@ -1005,16 +1005,11 @@ static int gc2375h_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int gc2375h_g_mbus_config(struct v4l2_subdev *sd,
static int gc2375h_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (GC2375H_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = GC2375H_LANES;
return 0;
}
@@ -1041,7 +1036,6 @@ static const struct v4l2_subdev_core_ops gc2375h_core_ops = {
static const struct v4l2_subdev_video_ops gc2375h_video_ops = {
.s_stream = gc2375h_s_stream,
.g_frame_interval = gc2375h_g_frame_interval,
.g_mbus_config = gc2375h_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops gc2375h_pad_ops = {
@@ -1050,6 +1044,7 @@ static const struct v4l2_subdev_pad_ops gc2375h_pad_ops = {
.enum_frame_interval = gc2375h_enum_frame_interval,
.get_fmt = gc2375h_get_fmt,
.set_fmt = gc2375h_set_fmt,
.get_mbus_config = gc2375h_g_mbus_config,
};
static const struct v4l2_subdev_ops gc2375h_subdev_ops = {

7
drivers/media/i2c/gc2385.c
View File

@@ -786,13 +786,8 @@ static int gc2385_enum_frame_interval(struct v4l2_subdev *sd,
static int gc2385_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (GC2385_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC2385_LANES;
return 0;
}

17
drivers/media/i2c/gc3003.c
View File

@@ -741,7 +741,7 @@ static const struct gc3003_mode supported_modes[] = {
.stream_on_reg_list = gc3003_stream_on_regs,
.stand_by_reg_list = gc3003_stand_by_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 320,
@@ -758,7 +758,7 @@ static const struct gc3003_mode supported_modes[] = {
.stream_on_reg_list = gc3003_stream_on_regs,
.stand_by_reg_list = gc3003_stand_by_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 1920,
@@ -775,7 +775,7 @@ static const struct gc3003_mode supported_modes[] = {
.stream_on_reg_list = gc3003_stream_on_regs,
.stand_by_reg_list = gc3003_stand_by_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1063,17 +1063,8 @@ static int gc3003_g_frame_interval(struct v4l2_subdev *sd,
static int gc3003_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc3003 *gc3003 = to_gc3003(sd);
const struct gc3003_mode *mode = gc3003->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (GC3003_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC3003_LANES;
return 0;
}

18
drivers/media/i2c/gc4023.c
View File

@@ -383,7 +383,7 @@ static const struct gc4023_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.reg_list = gc4023_linear10bit_2560x1440_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -728,22 +728,8 @@ static int gc4023_g_frame_interval(struct v4l2_subdev *sd,
static int gc4023_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc4023 *gc4023 = to_gc4023(sd);
const struct gc4023_mode *mode = gc4023->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (GC4023_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (GC4023_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC4023_LANES;
return 0;
}

13
drivers/media/i2c/gc4653.c
View File

@@ -383,7 +383,7 @@ static const struct gc4653_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
.reg_list = gc4653_linear10bit_2560x1440_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -676,17 +676,8 @@ static int gc4653_g_frame_interval(struct v4l2_subdev *sd,
static int gc4653_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc4653 *gc4653 = to_gc4653(sd);
const struct gc4653_mode *mode = gc4653->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (GC4653_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC4653_LANES;
return 0;
}

26
drivers/media/i2c/gc4663.c
View File

@@ -564,7 +564,7 @@ static const struct gc4663_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
.reg_list = gc4663_linear10bit_2560x1440_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 2560,
.height = 1440,
@@ -578,10 +578,10 @@ static const struct gc4663_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
.reg_list = gc4663_hdr10bit_2560x1440_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1007,22 +1007,8 @@ static int gc4663_g_frame_interval(struct v4l2_subdev *sd,
static int gc4663_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc4663 *gc4663 = to_gc4663(sd);
const struct gc4663_mode *mode = gc4663->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (GC4663_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (GC4663_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC4663_LANES;
return 0;
}

19
drivers/media/i2c/gc4c33.c
View File

@@ -1108,7 +1108,7 @@ static const struct gc4c33_mode supported_modes[] = {
.reg_list = gc4c33_linear10bit_2560x1440_regs,
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 1920,
.height = 1080,
@@ -1122,7 +1122,7 @@ static const struct gc4c33_mode supported_modes[] = {
.reg_list = gc4c33_linear10bit_1920x1080_regs,
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 1280,
.height = 720,
@@ -1136,7 +1136,7 @@ static const struct gc4c33_mode supported_modes[] = {
.reg_list = gc4c33_linear10bit_1280x720_regs,
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1518,19 +1518,8 @@ static int gc4c33_g_frame_interval(struct v4l2_subdev *sd,
static int gc4c33_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct gc4c33 *gc4c33 = to_gc4c33(sd);
const struct gc4c33_mode *mode = gc4c33->cur_mode;
u32 val = 1 << (GC4C33_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC4C33_LANES;
return 0;
}

10
drivers/media/i2c/gc5024.c
View File

@@ -870,7 +870,7 @@ static int gc5024_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
}
#endif
static int sensor_g_mbus_config(struct v4l2_subdev *sd,
static int sensor_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
struct gc5024 *sensor = to_gc5024(sd);
@@ -879,10 +879,8 @@ static int sensor_g_mbus_config(struct v4l2_subdev *sd,
dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
if (2 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = sensor->lane_num;
} else {
dev_err(&sensor->client->dev,
"unsupported lane_num(%d)\n", sensor->lane_num);
@@ -926,7 +924,6 @@ static const struct v4l2_subdev_core_ops gc5024_core_ops = {
};
static const struct v4l2_subdev_video_ops gc5024_video_ops = {
.g_mbus_config = sensor_g_mbus_config,
.s_stream = gc5024_s_stream,
.g_frame_interval = gc5024_g_frame_interval,
};
@@ -937,6 +934,7 @@ static const struct v4l2_subdev_pad_ops gc5024_pad_ops = {
.enum_frame_interval = gc5024_enum_frame_interval,
.get_fmt = gc5024_get_fmt,
.set_fmt = gc5024_set_fmt,
.get_mbus_config = sensor_g_mbus_config,
};
static const struct v4l2_subdev_ops gc5024_subdev_ops = {

8
drivers/media/i2c/gc5025.c
View File

@@ -1510,14 +1510,8 @@ static int gc5025_enum_frame_interval(struct v4l2_subdev *sd,
static int gc5025_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (GC5025_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = GC5025_LANES;
return 0;
}

4
drivers/media/i2c/gc5035.c
View File

@@ -972,9 +972,7 @@ static int sensor_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
if (2 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2.num_data_lanes = sensor->lane_num;
} else {
dev_err(&sensor->client->dev,
"unsupported lane_num(%d)\n", sensor->lane_num);

19
drivers/media/i2c/gc8034.c
View File

@@ -1158,7 +1158,7 @@ static const struct gc8034_mode supported_modes_2lane[] = {
.mipi_freq_idx = 1,
.global_reg_list = gc8034_global_regs_2lane,
.reg_list = gc8034_3264x2448_regs_2lane,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
#else
{
@@ -1174,7 +1174,7 @@ static const struct gc8034_mode supported_modes_2lane[] = {
.mipi_freq_idx = 0,
.global_reg_list = gc8034_global_regs_2lane,
.reg_list = gc8034_3264x2448_regs_2lane,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 1632,
@@ -1189,7 +1189,7 @@ static const struct gc8034_mode supported_modes_2lane[] = {
.mipi_freq_idx = 0,
.global_reg_list = gc8034_global_regs_2lane,
.reg_list = gc8034_1632x1224_regs_2lane,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
#endif
};
@@ -1208,7 +1208,7 @@ static const struct gc8034_mode supported_modes_4lane[] = {
.mipi_freq_idx = 0,
.global_reg_list = gc8034_global_regs_4lane,
.reg_list = gc8034_3264x2448_regs_4lane,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -2675,16 +2675,9 @@ static int gc8034_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
if (2 == sensor->lane_num) {
if (2 == sensor->lane_num || 4 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2.num_data_lanes = sensor->lane_num;
} else {
dev_err(&sensor->client->dev,
"unsupported lane_num(%d)\n", sensor->lane_num);

6
drivers/media/i2c/hi556.c
View File

@@ -759,12 +759,8 @@ static int hi556_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 1 << (HI556_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = HI556_LANES;
return 0;
}

7
drivers/media/i2c/imx214.c
View File

@@ -1456,14 +1456,9 @@ static int imx214_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
{
struct imx214 *imx214 = to_imx214(sd);
u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = lane_num;
return 0;
}

14
drivers/media/i2c/imx258.c
View File

@@ -684,7 +684,7 @@ static const struct imx258_mode supported_modes[] = {
.spd = &imx258_full_spd,
.ebd = &imx258_full_ebd,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
@@ -701,7 +701,7 @@ static const struct imx258_mode supported_modes[] = {
.spd = NULL,
.ebd = NULL,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -896,13 +896,13 @@ static int imx258_get_fmt(struct v4l2_subdev *sd,
fmt->format.height = mode->spd->height;
fmt->format.code = mode->spd->bus_fmt;
//Set the vc channel to be consistent with the valid data
fmt->reserved[0] = V4L2_MBUS_CSI2_CHANNEL_0;
fmt->reserved[0] = 0;
} else if (fmt->pad == imx258->ebd_id && mode->ebd) {
fmt->format.width = mode->ebd->width;
fmt->format.height = mode->ebd->height;
fmt->format.code = mode->ebd->bus_fmt;
//Set the vc channel to be consistent with the valid data
fmt->reserved[0] = V4L2_MBUS_CSI2_CHANNEL_0;
fmt->reserved[0] = 0;
}
}
mutex_unlock(&imx258->mutex);
@@ -1592,13 +1592,9 @@ static int imx258_enum_frame_interval(struct v4l2_subdev *sd,
static int imx258_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (IMX258_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = IMX258_LANES;
return 0;
}

9
drivers/media/i2c/imx307.c
View File

@@ -1196,13 +1196,12 @@ static int imx307_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx307 *imx307 = to_imx307(sd);
u32 val = 0;
val = 1 << (imx307->cur_mode->lanes - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = imx307->bus_cfg.bus_type;
config->flags = val;
if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2)
config->bus.mipi_csi1 = imx307->bus_cfg.bus.mipi_csi1;
else if (imx307->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY)
config->bus.mipi_csi2 = imx307->bus_cfg.bus.mipi_csi2;
return 0;
}

6
drivers/media/i2c/imx317.c
View File

@@ -1186,14 +1186,10 @@ static int imx317_enum_frame_interval(struct v4l2_subdev *sd,
static int imx317_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
struct imx317 *imx317 = to_imx317(sd);
val = 1 << (imx317->lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = imx317->lane_num;
return 0;
}

2
drivers/media/i2c/imx323.c
View File

@@ -708,7 +708,7 @@ static int imx323_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_BT656;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_HIGH |
V4L2_MBUS_PCLK_SAMPLE_FALLING;
return 0;

10
drivers/media/i2c/imx327.c
View File

@@ -874,14 +874,12 @@ static int imx327_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx327 *imx327 = to_imx327(sd);
u32 val = 0;
val = 1 << (IMX327_4LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = imx327->bus_cfg.bus_type;
config->flags = val;
if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2)
config->bus.mipi_csi1 = imx327->bus_cfg.bus.mipi_csi1;
else if (imx327->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY)
config->bus.mipi_csi2 = imx327->bus_cfg.bus.mipi_csi2;
return 0;
}

30
drivers/media/i2c/imx334.c
View File

@@ -535,7 +535,7 @@ static const struct imx334_mode supported_modes[] = {
.vclk_freq = IMX334_XVCLK_FREQ_37,
.bpp = 10,
.mipi_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 3864,
.height = 2180,
@@ -553,10 +553,10 @@ static const struct imx334_mode supported_modes[] = {
.vclk_freq = IMX334_XVCLK_FREQ_37,
.bpp = 10,
.mipi_freq_idx = 2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
}, {
.width = 3864,
.height = 2180,
@@ -574,7 +574,7 @@ static const struct imx334_mode supported_modes[] = {
.vclk_freq = IMX334_XVCLK_FREQ_37,
.bpp = 12,
.mipi_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 3864,
.height = 2180,
@@ -592,10 +592,10 @@ static const struct imx334_mode supported_modes[] = {
.vclk_freq = IMX334_XVCLK_FREQ_74,
.bpp = 12,
.mipi_freq_idx = 2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -851,15 +851,7 @@ static int imx334_g_frame_interval(struct v4l2_subdev *sd,
static int imx334_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx334 *imx334 = to_imx334(sd);
const struct imx334_mode *mode = imx334->cur_mode;
u32 val = 0;
val = 1 << (IMX334_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->flags = (mode->hdr_mode == NO_HDR) ? val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
config->bus.mipi_csi2.num_data_lanes = IMX334_LANES;
config->type = V4L2_MBUS_CSI2_DPHY;
return 0;
}

29
drivers/media/i2c/imx335.c
View File

@@ -562,10 +562,10 @@ static const struct imx335_mode supported_modes[] = {
.reg_list = imx335_hdr2_10bit_2592x1944_regs,
.hdr_mode = HDR_X2,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
/* 1H period = 3.70us */
@@ -586,10 +586,10 @@ static const struct imx335_mode supported_modes[] = {
.reg_list = imx335_hdr3_10bit_2592x1944_regs,
.hdr_mode = HDR_X3,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
.vc[PAD0] = 2,
.vc[PAD1] = 1,//M->csi wr0
.vc[PAD2] = 0,//L->csi wr0
.vc[PAD3] = 2,//S->csi wr2
},
};
@@ -816,19 +816,8 @@ static int imx335_g_frame_interval(struct v4l2_subdev *sd,
static int imx335_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
struct imx335 *imx335 = to_imx335(sd);
const struct imx335_mode *mode = imx335->cur_mode;
val = 1 << (IMX335_4LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = IMX335_4LANES;
return 0;
}

35
drivers/media/i2c/imx347.c
View File

@@ -702,7 +702,7 @@ static const struct imx347_mode supported_modes[] = {
.vts_def = 0x07bc,
.reg_list = imx347_linear_10bit_2688x1520_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
.bpp = 10,
},
{
@@ -718,10 +718,10 @@ static const struct imx347_mode supported_modes[] = {
.vts_def = 0x07bc * 2,
.reg_list = imx347_hdr_2x_10bit_2688x1520_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
.bpp = 10,
},
{
@@ -737,7 +737,7 @@ static const struct imx347_mode supported_modes[] = {
.vts_def = 0x0A6B,
.reg_list = imx347_linear_12bit_2688x1520_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
.bpp = 12,
},
{
@@ -753,10 +753,10 @@ static const struct imx347_mode supported_modes[] = {
.vts_def = 0x0640 * 2,
.reg_list = imx347_hdr_2x_12bit_2688x1520_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
.bpp = 12,
},
};
@@ -1023,26 +1023,17 @@ static int imx347_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
{
struct imx347 *imx347 = to_imx347(sd);
const struct imx347_mode *mode = imx347->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR) {
if (mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10)
val = 1 << (IMX347_2LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2.num_data_lanes = IMX347_2LANES;
else
val = 1 << (IMX347_4LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2.num_data_lanes = IMX347_4LANES;
}
if (mode->hdr_mode == HDR_X2)
val = 1 << (IMX347_4LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->bus.mipi_csi2.num_data_lanes = IMX347_4LANES;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
return 0;
}

25
drivers/media/i2c/imx378.c
View File

@@ -1768,7 +1768,7 @@ static const struct imx378_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.reg_list = imx378_linear_10_3840x2160_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 4056,
.height = 3040,
@@ -1782,7 +1782,7 @@ static const struct imx378_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.reg_list = imx378_linear_10_4056x3040_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 2028,
.height = 1520,
@@ -1796,7 +1796,7 @@ static const struct imx378_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
.reg_list = imx378_linear_12_2028x1520_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 4056,
.height = 3040,
@@ -1810,7 +1810,7 @@ static const struct imx378_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
.reg_list = imx378_linear_12_4056x3040_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -2091,23 +2091,8 @@ static int imx378_g_frame_interval(struct v4l2_subdev *sd,
static int imx378_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx378 *imx378 = to_imx378(sd);
const struct imx378_mode *mode = imx378->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (IMX378_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (IMX378_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = IMX378_LANES;
return 0;
}

67
drivers/media/i2c/imx415.c
View File

@@ -778,7 +778,7 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.mipi_freq_idx = 1,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -800,10 +800,10 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.mipi_freq_idx = 2,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -825,10 +825,10 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = HDR_X3,
.mipi_freq_idx = 2,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
.vc[PAD0] = 2,
.vc[PAD1] = 1,//M->csi wr0
.vc[PAD2] = 0,//L->csi wr0
.vc[PAD3] = 2,//S->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -850,10 +850,10 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = HDR_X3,
.mipi_freq_idx = 3,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
.vc[PAD0] = 2,
.vc[PAD1] = 1,//M->csi wr0
.vc[PAD2] = 0,//L->csi wr0
.vc[PAD3] = 2,//S->csi wr2
},
{
/* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */
@@ -872,7 +872,7 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.mipi_freq_idx = 1,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
@@ -894,10 +894,10 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.mipi_freq_idx = 3,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
@@ -919,10 +919,10 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = HDR_X3,
.mipi_freq_idx = 3,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
.vc[PAD0] = 2,
.vc[PAD1] = 1,//M->csi wr0
.vc[PAD2] = 0,//L->csi wr0
.vc[PAD3] = 2,//S->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
@@ -940,7 +940,7 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.mipi_freq_idx = 0,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
@@ -962,10 +962,10 @@ static const struct imx415_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.mipi_freq_idx = 1,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1224,19 +1224,8 @@ static int imx415_g_frame_interval(struct v4l2_subdev *sd,
static int imx415_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx415 *imx415 = to_imx415(sd);
const struct imx415_mode *mode = imx415->cur_mode;
u32 val = 0;
val = 1 << (IMX415_4LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = IMX415_4LANES;
return 0;
}

49
drivers/media/i2c/imx464.c
View File

@@ -1365,7 +1365,7 @@ static const struct IMX464_mode supported_modes[] = {
.mclk = 37125000,
.reg_list = IMX464_linear_10bit_2688x1520_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
@@ -1383,10 +1383,10 @@ static const struct IMX464_mode supported_modes[] = {
.mclk = 37125000,
.reg_list = IMX464_hdr_2x_10bit_2688x1520_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
@@ -1412,10 +1412,10 @@ static const struct IMX464_mode supported_modes[] = {
.mclk = 37125000,
.reg_list = IMX464_hdr_3x_10bit_2688x1520_regs,
.hdr_mode = HDR_X3,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr1
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
.vc[PAD0] = 2,
.vc[PAD1] = 1,//M->csi wr0
.vc[PAD2] = 0,//L->csi wr1
.vc[PAD3] = 2,//S->csi wr2
},
};
@@ -1436,7 +1436,7 @@ static const struct IMX464_mode supported_modes_2lane[] = {
.mclk = 24000000,
.reg_list = IMX464_linear_10bit_2688x1520_2lane_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
@@ -1454,10 +1454,10 @@ static const struct IMX464_mode supported_modes_2lane[] = {
.mclk = 24000000,
.reg_list = IMX464_hdr_2x_10bit_2688x1520_2lane_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1695,29 +1695,10 @@ static int IMX464_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct IMX464 *IMX464 = to_IMX464(sd);
const struct IMX464_mode *mode = IMX464->cur_mode;
u32 val = 0;
u32 lane_num = IMX464->bus_cfg.bus.mipi_csi2.num_data_lanes;
if (mode->hdr_mode == NO_HDR) {
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
if (mode->hdr_mode == HDR_X2)
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1 |
V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = lane_num;
return 0;
}

49
drivers/media/i2c/imx492.c
View File

@@ -683,7 +683,7 @@ static const struct imx492_mode supported_modes[] = {
.mclk = 24000000,
.reg_list = imx492_linear_12bit_8192x4320_4lane_mode1_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
@@ -701,7 +701,7 @@ static const struct imx492_mode supported_modes[] = {
.mclk = 24000000,
.reg_list = imx492_linear_10bit_8192x4320_4lane_mode2_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}
};
@@ -821,7 +821,7 @@ imx492_find_best_fit(struct imx492 *imx492, struct v4l2_subdev_format *fmt)
}
static int imx492_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct imx492 *imx492 = to_IMX492(sd);
@@ -838,7 +838,7 @@ static int imx492_set_fmt(struct v4l2_subdev *sd,
fmt->format.field = V4L2_FIELD_NONE;
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
*v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
#else
mutex_unlock(&imx492->mutex);
return -ENOTTY;
@@ -865,7 +865,7 @@ static int imx492_set_fmt(struct v4l2_subdev *sd,
}
static int imx492_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct imx492 *imx492 = to_IMX492(sd);
@@ -874,7 +874,7 @@ static int imx492_get_fmt(struct v4l2_subdev *sd,
mutex_lock(&imx492->mutex);
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
fmt->format = *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
#else
mutex_unlock(&imx492->mutex);
return -ENOTTY;
@@ -895,7 +895,7 @@ static int imx492_get_fmt(struct v4l2_subdev *sd,
}
static int imx492_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct imx492 *imx492 = to_IMX492(sd);
@@ -908,7 +908,7 @@ static int imx492_enum_mbus_code(struct v4l2_subdev *sd,
}
static int imx492_enum_frame_sizes(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
struct imx492 *imx492 = to_IMX492(sd);
@@ -942,29 +942,10 @@ static int imx492_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx492 *imx492 = to_IMX492(sd);
const struct imx492_mode *mode = imx492->cur_mode;
u32 val = 0;
u32 lane_num = imx492->bus_cfg.bus.mipi_csi2.num_data_lanes;
if (mode->hdr_mode == NO_HDR) {
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
if (mode->hdr_mode == HDR_X2)
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1 |
V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = lane_num;
return 0;
}
@@ -1418,7 +1399,7 @@ static int imx492_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct imx492 *imx492 = to_IMX492(sd);
struct v4l2_mbus_framefmt *try_fmt =
v4l2_subdev_get_try_format(sd, fh->pad, 0);
v4l2_subdev_get_try_format(sd, fh->state, 0);
const struct imx492_mode *def_mode = &imx492->support_modes[0];
mutex_lock(&imx492->mutex);
@@ -1436,7 +1417,7 @@ static int imx492_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
#endif
static int imx492_enum_frame_interval(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_interval_enum *fie)
{
struct imx492 *imx492 = to_IMX492(sd);
@@ -1469,7 +1450,7 @@ static int imx492_enum_frame_interval(struct v4l2_subdev *sd,
* to the alignment rules.
*/
static int imx492_get_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_selection *sel)
{
struct imx492 *imx492 = to_IMX492(sd);
@@ -1905,7 +1886,7 @@ static int imx492_probe(struct i2c_client *client,
snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
imx492->module_index, facing,
IMX492_NAME, dev_name(sd->dev));
ret = v4l2_async_register_subdev_sensor_common(sd);
ret = v4l2_async_register_subdev_sensor(sd);
if (ret) {
dev_err(dev, "v4l2 async register subdev failed\n");
goto err_clean_entity;
@@ -1931,7 +1912,7 @@ err_destroy_mutex:
return ret;
}
static int imx492_remove(struct i2c_client *client)
static void imx492_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct imx492 *imx492 = to_IMX492(sd);
@@ -1947,8 +1928,6 @@ static int imx492_remove(struct i2c_client *client)
if (!pm_runtime_status_suspended(&client->dev))
__imx492_power_off(imx492);
pm_runtime_set_suspended(&client->dev);
return 0;
}
#if IS_ENABLED(CONFIG_OF)

25
drivers/media/i2c/imx577.c
View File

@@ -962,7 +962,7 @@ static const struct imx577_mode supported_modes[] = {
.reg_list = imx577_linear_10bit_4056x3040_30fps_regs,
.hdr_mode = NO_HDR,
.link_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 4056,
@@ -979,10 +979,10 @@ static const struct imx577_mode supported_modes[] = {
.reg_list = imx577_hdr2_10bit_4056x3040_30fps_regs,
.link_freq_idx = 0,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
.width = 4056,
@@ -999,7 +999,7 @@ static const struct imx577_mode supported_modes[] = {
.reg_list = imx577_linear_10bit_4056x3040_60fps_regs,
.hdr_mode = NO_HDR,
.link_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 4056,
@@ -1016,7 +1016,7 @@ static const struct imx577_mode supported_modes[] = {
.reg_list = imx577_linear_12bit_4056x3040_40fps_regs,
.hdr_mode = NO_HDR,
.link_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1931,18 +1931,9 @@ static int imx577_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
struct imx577 *imx577 = to_imx577(sd);
const struct imx577_mode *mode = imx577->cur_mode;
u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2 = imx577->bus_cfg.bus.mipi_csi2;
return 0;
}

27
drivers/media/i2c/imx586.c
View File

@@ -812,7 +812,7 @@ static const struct imx586_mode supported_modes[] = {
.reg_list = imx586_linear_10bit_4000x3000_30fps_nopd_regs,
.hdr_mode = NO_HDR,
.mipi_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 8000,
@@ -829,7 +829,7 @@ static const struct imx586_mode supported_modes[] = {
.reg_list = imx586_linear_10bit_full_raw_6fps_regs,
.hdr_mode = NO_HDR,
.mipi_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 8000,
@@ -846,7 +846,7 @@ static const struct imx586_mode supported_modes[] = {
.reg_list = imx586_linear_10bit_full_remosaic_6fps_regs,
.hdr_mode = NO_HDR,
.mipi_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 8000,
@@ -863,7 +863,7 @@ static const struct imx586_mode supported_modes[] = {
.reg_list = imx586_linear_10bit_full_remosaic_10fps_regs,
.hdr_mode = NO_HDR,
.mipi_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1141,23 +1141,8 @@ static int imx586_g_frame_interval(struct v4l2_subdev *sd,
static int imx586_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct imx586 *imx586 = to_imx586(sd);
const struct imx586_mode *mode = imx586->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (IMX586_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (IMX586_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = IMX586_LANES;
return 0;
}
@@ -1264,7 +1249,7 @@ static int imx586_get_channel_info(struct imx586 *imx586, struct rkmodule_channe
return -EINVAL;
if (ch_info->index == imx586->spd_id && mode->spd) {
ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_0;
ch_info->vc = 0;
ch_info->width = mode->spd->width;
ch_info->height = mode->spd->height;
ch_info->bus_fmt = mode->spd->bus_fmt;

21
drivers/media/i2c/it6616.c
View File

@@ -3641,26 +3641,7 @@ static int it6616_g_mbus_config(struct v4l2_subdev *sd,
struct it6616 *it6616 = to_it6616(sd);
cfg->type = V4L2_MBUS_CSI2_DPHY;
cfg->flags = V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_0;
switch (it6616->csi_lanes_in_use) {
case 1:
cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
break;
case 2:
cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
break;
case 3:
cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
break;
case 4:
cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
break;
default:
return -EINVAL;
}
cfg->bus.mipi_csi2.num_data_lanes = it6616->csi_lanes_in_use;
return 0;
}

3
drivers/media/i2c/jaguar1_drv/jaguar1_v4l2.c
View File

@@ -509,8 +509,7 @@ static int jaguar1_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *cfg)
{
cfg->type = V4L2_MBUS_CSI2_DPHY;
cfg->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNELS;
cfg->bus.mipi_csi2.num_data_lanes = 4;
return 0;
}

32
drivers/media/i2c/jx_f37.c
View File

@@ -378,7 +378,7 @@ static const struct jx_f37_mode supported_modes[] = {
.vts_def = 0x0465,
.reg_list = jx_f37_1080p_linear_1lane_30fps,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 1920,
@@ -392,10 +392,10 @@ static const struct jx_f37_mode supported_modes[] = {
.vts_def = 0x08ca,
.reg_list = jx_f37_1080p_hdr_1lane_15fps,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -932,25 +932,11 @@ static int jx_f37_g_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int jx_f37_g_mbus_config(struct v4l2_subdev *sd,
static int jx_f37_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
struct jx_f37 *jx_f37 = to_jx_f37(sd);
const struct jx_f37_mode *mode = jx_f37->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (JX_F37_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
else if (mode->hdr_mode == HDR_X2)
val = 1 << (JX_F37_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = JX_F37_LANES;
return 0;
}
@@ -1213,7 +1199,6 @@ static const struct v4l2_subdev_core_ops jx_f37_core_ops = {
static const struct v4l2_subdev_video_ops jx_f37_video_ops = {
.s_stream = jx_f37_s_stream,
.g_frame_interval = jx_f37_g_frame_interval,
.g_mbus_config = jx_f37_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops jx_f37_pad_ops = {
@@ -1222,6 +1207,7 @@ static const struct v4l2_subdev_pad_ops jx_f37_pad_ops = {
.enum_frame_interval = jx_f37_enum_frame_interval,
.get_fmt = jx_f37_get_fmt,
.set_fmt = jx_f37_set_fmt,
.get_mbus_config = jx_f37_g_mbus_config,
};
static const struct v4l2_subdev_ops jx_f37_subdev_ops = {

13
drivers/media/i2c/jx_h62.c
View File

@@ -804,16 +804,11 @@ static int jx_h62_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int jx_h62_g_mbus_config(struct v4l2_subdev *sd,
static int jx_h62_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (JX_H62_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = JX_H62_LANES;
return 0;
}
@@ -840,7 +835,6 @@ static const struct v4l2_subdev_core_ops jx_h62_core_ops = {
static const struct v4l2_subdev_video_ops jx_h62_video_ops = {
.s_stream = jx_h62_s_stream,
.g_frame_interval = jx_h62_g_frame_interval,
.g_mbus_config = jx_h62_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops jx_h62_pad_ops = {
@@ -849,6 +843,7 @@ static const struct v4l2_subdev_pad_ops jx_h62_pad_ops = {
.enum_frame_interval = jx_h62_enum_frame_interval,
.get_fmt = jx_h62_get_fmt,
.set_fmt = jx_h62_set_fmt,
.get_mbus_config = jx_h62_g_mbus_config,
};
static const struct v4l2_subdev_ops jx_h62_subdev_ops = {

13
drivers/media/i2c/jx_h65.c
View File

@@ -903,16 +903,11 @@ static int jx_h65_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int jx_h65_g_mbus_config(struct v4l2_subdev *sd,
static int jx_h65_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (JX_H65_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = JX_H65_LANES;
return 0;
}
@@ -939,7 +934,6 @@ static const struct v4l2_subdev_core_ops jx_h65_core_ops = {
static const struct v4l2_subdev_video_ops jx_h65_video_ops = {
.s_stream = jx_h65_s_stream,
.g_frame_interval = jx_h65_g_frame_interval,
.g_mbus_config = jx_h65_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops jx_h65_pad_ops = {
@@ -948,6 +942,7 @@ static const struct v4l2_subdev_pad_ops jx_h65_pad_ops = {
.enum_frame_interval = jx_h65_enum_frame_interval,
.get_fmt = jx_h65_get_fmt,
.set_fmt = jx_h65_set_fmt,
.get_mbus_config = jx_h65_g_mbus_config,
};
static const struct v4l2_subdev_ops jx_h65_subdev_ops = {

17
drivers/media/i2c/jx_k17.c
View File

@@ -289,7 +289,7 @@ static const struct jx_k17_mode supported_modes[] = {
.reg_list = jx_k17_2560x1440_2lane_regs,
.bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -540,21 +540,8 @@ static int jx_k17_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct jx_k17 *jx_k17 = to_jx_k17(sd);
const struct jx_k17_mode *mode = jx_k17->cur_mode;
u32 val;
val = 1 << (JX_K17_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = JX_K17_LANES;
return 0;
}

20
drivers/media/i2c/lt6911uxc.c
View File

@@ -754,25 +754,7 @@ static int lt6911uxc_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct lt6911uxc *lt6911uxc = to_state(sd);
cfg->type = V4L2_MBUS_CSI2_DPHY;
cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | V4L2_MBUS_CSI2_CHANNEL_0;
switch (lt6911uxc->csi_lanes_in_use) {
case 1:
cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
break;
case 2:
cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
break;
case 3:
cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
break;
case 4:
cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
break;
default:
return -EINVAL;
}
cfg->bus.mipi_csi2 = lt6911uxc->bus;
return 0;
}

8
drivers/media/i2c/lt6911uxe.c
View File

@@ -1114,15 +1114,9 @@ static int lt6911uxe_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad, struct v4l2_mbus_config *cfg)
{
struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
u32 lane_num = lt6911uxe->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
cfg->type = lt6911uxe->bus_cfg.bus_type;
cfg->flags = val;
cfg->bus.mipi_csi2 = lt6911uxe->bus_cfg.bus.mipi_csi2;
return 0;
}

21
drivers/media/i2c/lt7911d.c
View File

@@ -725,26 +725,7 @@ static int lt7911d_g_mbus_config(struct v4l2_subdev *sd,
struct lt7911d_state *lt7911d = to_state(sd);
cfg->type = V4L2_MBUS_CSI2_DPHY;
cfg->flags = V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_0;
switch (lt7911d->csi_lanes_in_use) {
case 1:
cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
break;
case 2:
cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
break;
case 3:
cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
break;
case 4:
cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
break;
default:
return -EINVAL;
}
cfg->bus.mipi_csi2 = lt7911d->bus;
return 0;
}

8
drivers/media/i2c/lt7911uxc.c
View File

@@ -936,15 +936,9 @@ static int lt7911uxc_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad, struct v4l2_mbus_config *cfg)
{
struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
u32 lane_num = lt7911uxc->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
cfg->type = lt7911uxc->bus_cfg.bus_type;
cfg->flags = val;
cfg->bus.mipi_csi2 = lt7911uxc->bus_cfg.bus.mipi_csi2;
return 0;
}

4
drivers/media/i2c/lt8619c.c
View File

@@ -1149,11 +1149,11 @@ static int lt8619c_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
cfg->type = V4L2_MBUS_BT656;
if (lt8619c->clk_ddrmode_en) {
cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
cfg->bus.parallel.flags = RKMODULE_CAMERA_BT656_CHANNELS |
V4L2_MBUS_PCLK_SAMPLE_RISING |
V4L2_MBUS_PCLK_SAMPLE_FALLING;
} else {
cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
cfg->bus.parallel.flags = RKMODULE_CAMERA_BT656_CHANNELS |
V4L2_MBUS_PCLK_SAMPLE_RISING;
}

28
drivers/media/i2c/nvp6188.c
View File

@@ -812,10 +812,10 @@ static struct nvp6188_mode supported_modes[] = {
.global_reg_list = common_setting_1458M_regs,
.mipi_freq_idx = 0,
.bpp = 8,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
{
.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
@@ -828,10 +828,10 @@ static struct nvp6188_mode supported_modes[] = {
.global_reg_list = common_setting_1458M_regs,
.mipi_freq_idx = 0,
.bpp = 8,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
{
.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
@@ -844,10 +844,10 @@ static struct nvp6188_mode supported_modes[] = {
.global_reg_list = common_setting_1458M_regs,
.mipi_freq_idx = 0,
.bpp = 8,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
};
@@ -1123,8 +1123,7 @@ static int nvp6188_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *cfg)
{
cfg->type = V4L2_MBUS_CSI2_DPHY;
cfg->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNELS;
cfg->bus.mipi_csi2.num_data_lanes = 4;
return 0;
}
@@ -2840,7 +2839,6 @@ static struct snd_soc_component_driver nvp6188_codec_driver = {
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
.non_legacy_dai_naming = 1,
};
static int check_chip_id(struct i2c_client *client){

12
drivers/media/i2c/os02g10.c
View File

@@ -295,7 +295,7 @@ static const struct os02g10_mode supported_modes[] = {
.vts_def = 0x0516,
.reg_list = os02g10_linear10bit_1920x1080_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -533,17 +533,9 @@ static int os02g10_g_frame_interval(struct v4l2_subdev *sd,
static int os02g10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
struct os02g10 *os02g10 = to_os02g10(sd);
const struct os02g10_mode *mode = os02g10->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OS02G10_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OS02G10_LANES;
return 0;
}

13
drivers/media/i2c/os03b10.c
View File

@@ -300,7 +300,7 @@ static const struct os03b10_mode supported_modes[] = {
.vts_def = 0x052d,
.reg_list = os03b10_linear10bit_2304x1296_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -541,17 +541,8 @@ static int os03b10_g_frame_interval(struct v4l2_subdev *sd,
static int os03b10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
struct os03b10 *os03b10 = to_os03b10(sd);
const struct os03b10_mode *mode = os03b10->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OS03B10_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OS03B10_LANES;
return 0;
}

52
drivers/media/i2c/os04a10.c
View File

@@ -1180,7 +1180,7 @@ static const struct os04a10_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.link_freq_idx = 0,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
@@ -1200,10 +1200,10 @@ static const struct os04a10_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.link_freq_idx = 0,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -1221,7 +1221,7 @@ static const struct os04a10_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.link_freq_idx = 1,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -1239,10 +1239,10 @@ static const struct os04a10_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.link_freq_idx = 1,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -1260,10 +1260,10 @@ static const struct os04a10_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.link_freq_idx = 1,
.bpp = 12,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1284,7 +1284,7 @@ static const struct os04a10_mode supported_modes_2lane[] = {
.hdr_mode = NO_HDR,
.link_freq_idx = 0,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
@@ -1304,10 +1304,10 @@ static const struct os04a10_mode supported_modes_2lane[] = {
.hdr_mode = HDR_X2,
.link_freq_idx = 2,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1576,22 +1576,10 @@ static int os04a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct os04a10 *os04a10 = to_os04a10(sd);
const struct os04a10_mode *mode = os04a10->cur_mode;
u32 val = 0;
u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
if (mode->hdr_mode == NO_HDR)
val = 1 << (lanes - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (lanes - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = lanes;
return 0;
}

26
drivers/media/i2c/os05a20.c
View File

@@ -656,7 +656,7 @@ static const struct os05a20_mode supported_modes[] = {
.vts_def = 0x0dad,
.reg_list = os05a20_linear12bit_2688x1944_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -671,10 +671,10 @@ static const struct os05a20_mode supported_modes[] = {
.vts_def = 0x09c4,
.reg_list = os05a20_hdr12bit_2688x1944_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -928,22 +928,8 @@ static int os05a20_g_frame_interval(struct v4l2_subdev *sd,
static int os05a20_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct os05a20 *os05a20 = to_os05a20(sd);
const struct os05a20_mode *mode = os05a20->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OS05A20_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (OS05A20_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OS05A20_LANES;
return 0;
}

7
drivers/media/i2c/os08a20.c
View File

@@ -1117,13 +1117,8 @@ static int os08a20_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OS08A20_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OS08A20_LANES;
return 0;
}

18
drivers/media/i2c/ov02b10.c
View File

@@ -290,7 +290,7 @@ static const struct ov02b10_mode supported_modes[] = {
.vts_def = 0x04c4,
.reg_list = ov02b10_linear10bit_1600x1200_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -534,22 +534,8 @@ static int ov02b10_g_frame_interval(struct v4l2_subdev *sd,
static int ov02b10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov02b10 *ov02b10 = to_ov02b10(sd);
const struct ov02b10_mode *mode = ov02b10->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OV02B10_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (OV02B10_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV02B10_LANES;
return 0;
}

26
drivers/media/i2c/ov02k10.c
View File

@@ -553,7 +553,7 @@ static const struct ov02k10_mode supported_modes[] = {
.vts_def = 0x0b7c,
.reg_list = ov02k10_linear12bit_1920x1080_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -569,10 +569,10 @@ static const struct ov02k10_mode supported_modes[] = {
.vts_def = 0x06a8,
.reg_list = ov02k10_hdr12bit_1920x1080_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -837,22 +837,8 @@ static int ov02k10_g_frame_interval(struct v4l2_subdev *sd,
static int ov02k10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov02k10 *ov02k10 = to_ov02k10(sd);
const struct ov02k10_mode *mode = ov02k10->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OV02K10_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (OV02K10_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV02K10_LANES;
return 0;
}

20
drivers/media/i2c/ov12d2q.c
View File

@@ -1943,7 +1943,7 @@ static const struct ov12d2q_mode supported_modes[] = {
.vts_def = 0x0570,
.reg_list = ov12d2q_2256x1256_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
@@ -1958,7 +1958,7 @@ static const struct ov12d2q_mode supported_modes[] = {
.vts_def = 0x0ae0,
.reg_list = ov12d2q_4512x2512_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -2224,22 +2224,8 @@ static int ov12d2q_g_frame_interval(struct v4l2_subdev *sd,
static int ov12d2q_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov12d2q *ov12d2q = to_ov12d2q(sd);
const struct ov12d2q_mode *mode = ov12d2q->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OV12D2Q_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (OV12D2Q_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV12D2Q_LANES;
return 0;
}

7
drivers/media/i2c/ov13850.c
View File

@@ -1246,13 +1246,8 @@ static int ov13850_enum_frame_interval(struct v4l2_subdev *sd,
static int ov13850_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV13850_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV13850_LANES;
return 0;
}

14
drivers/media/i2c/ov13855.c
View File

@@ -1570,17 +1570,9 @@ static int ov13855_enum_frame_interval(struct v4l2_subdev *sd,
static int ov13855_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
if (2 == OV13855_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == OV13855_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV13855_LANES;
return 0;
}

17
drivers/media/i2c/ov16a10.c
View File

@@ -915,7 +915,7 @@ static const struct ov16a10_mode supported_modes[] = {
.reg_list = ov16a10_4656x3496_30fps_regs,
.link_freq_idx = 0,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 2328,
@@ -931,7 +931,7 @@ static const struct ov16a10_mode supported_modes[] = {
.reg_list = ov16a10_2328x1748_30fps_regs,
.link_freq_idx = 0,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1611,17 +1611,8 @@ static int ov16a10_enum_frame_interval(struct v4l2_subdev *sd,
static int ov16a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
if (2 == OV16A10_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == OV16A10_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV16A10_LANES;
return 0;
}

17
drivers/media/i2c/ov16a1q.c
View File

@@ -962,7 +962,7 @@ static const struct ov16a1q_mode supported_modes[] = {
.reg_list = ov16a1q_4656x3496_30fps_regs,
.link_freq_idx = 0,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 2328,
@@ -978,7 +978,7 @@ static const struct ov16a1q_mode supported_modes[] = {
.reg_list = ov16a1q_2328x1748_30fps_regs,
.link_freq_idx = 1,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1659,17 +1659,8 @@ static int ov16a1q_enum_frame_interval(struct v4l2_subdev *sd,
static int ov16a1q_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
if (2 == OV16A1Q_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == OV16A1Q_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV16A1Q_LANES;
return 0;
}

36
drivers/media/i2c/ov2718.c
View File

@@ -7590,7 +7590,7 @@ static const struct ov2718_mode supported_modes[] = {
.vts_def = 0x0466,
.hdr_mode = NO_HDR,
.reg_list = ov2718_linear12bit_init_tab_1920_1080,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -7605,10 +7605,10 @@ static const struct ov2718_mode supported_modes[] = {
.vts_def = 0x0466,
.hdr_mode = HDR_X2,
.reg_list = ov2718_hdr12bit_init_tab_1920_1080,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD0] = 1,
.vc[PAD1] = 0,
.vc[PAD2] = 1,
.vc[PAD3] = 1,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
@@ -7623,7 +7623,7 @@ static const struct ov2718_mode supported_modes[] = {
.vts_def = 0x0466,
.hdr_mode = NO_HDR,
.reg_list = ov2718_linear10bit_init_tab_1920_1080,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
@@ -7638,10 +7638,10 @@ static const struct ov2718_mode supported_modes[] = {
.vts_def = 0x0466,
.hdr_mode = HDR_X2,
.reg_list = ov2718_hdr10bit_init_tab_1920_1080,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD0] = 1,
.vc[PAD1] = 0,
.vc[PAD2] = 1,
.vc[PAD3] = 1,
}
};
@@ -7991,22 +7991,8 @@ static void ov2718_get_hcg_reg(u32 gain, u32 *again_reg, u32 *dgain_reg)
static int ov2718_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov2718 *ov2718 = to_ov2718(sd);
const struct ov2718_mode *mode = ov2718->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (OV2718_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (OV2718_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV2718_LANES;
return 0;
}

13
drivers/media/i2c/ov2735.c
View File

@@ -843,16 +843,11 @@ static int ov2735_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int ov2735_g_mbus_config(struct v4l2_subdev *sd,
static int ov2735_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV2735_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV2735_LANES;
return 0;
}
@@ -878,7 +873,6 @@ static const struct v4l2_subdev_core_ops ov2735_core_ops = {
static const struct v4l2_subdev_video_ops ov2735_video_ops = {
.s_stream = ov2735_s_stream,
.g_mbus_config = ov2735_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops ov2735_pad_ops = {
@@ -887,6 +881,7 @@ static const struct v4l2_subdev_pad_ops ov2735_pad_ops = {
.enum_frame_interval = ov2735_enum_frame_interval,
.get_fmt = ov2735_get_fmt,
.set_fmt = ov2735_set_fmt,
.get_mbus_config = ov2735_g_mbus_config,
};
static const struct v4l2_subdev_ops ov2735_subdev_ops = {

29
drivers/media/i2c/ov2775.c
View File

@@ -3817,7 +3817,7 @@ static const struct ov2775_mode supported_modes[] = {
.bpp = 12,
.lane = 4,
.reg_list = ov2775_linear12bit_init_tab_1920_1080,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
@@ -3834,10 +3834,10 @@ static const struct ov2775_mode supported_modes[] = {
.bpp = 12,
.lane = 4,
.reg_list = ov2775_hdr12bit_init_tab_1920_1080,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD0] = 1,
.vc[PAD1] = 0,
.vc[PAD2] = 1,
.vc[PAD3] = 1,
},
};
@@ -4178,25 +4178,14 @@ static void ov2775_get_hcg_reg(u32 gain, u32 *again_reg, u32 *dgain_reg)
}
}
static int ov2775_g_mbus_config(struct v4l2_subdev *sd,
static int ov2775_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
struct ov2775 *ov2775 = to_ov2775(sd);
const struct ov2775_mode *mode = ov2775->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (mode->lane - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (mode->lane - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = mode->lane;
return 0;
}
@@ -4770,7 +4759,6 @@ static const struct v4l2_subdev_internal_ops ov2775_internal_ops = {
static const struct v4l2_subdev_video_ops ov2775_video_ops = {
.s_stream = ov2775_s_stream,
.g_frame_interval = ov2775_g_frame_interval,
.g_mbus_config = ov2775_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops ov2775_pad_ops = {
@@ -4779,6 +4767,7 @@ static const struct v4l2_subdev_pad_ops ov2775_pad_ops = {
.enum_frame_interval = ov2775_enum_frame_interval,
.get_fmt = ov2775_get_fmt,
.set_fmt = ov2775_set_fmt,
.get_mbus_config = ov2775_g_mbus_config,
};
static const struct v4l2_subdev_core_ops ov2775_core_ops = {

23
drivers/media/i2c/ov4686.c
View File

@@ -465,7 +465,7 @@ static const struct OV4686_mode supported_modes[] = {
.vts_def = 0x0612,
.reg_list = OV4686_linear_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 2688,
.height = 1520,
@@ -478,10 +478,10 @@ static const struct OV4686_mode supported_modes[] = {
.vts_def = 0x0612,
.reg_list = OV4686_hdr_x2_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -726,19 +726,8 @@ static int OV4686_g_frame_interval(struct v4l2_subdev *sd,
static int OV4686_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct OV4686 *OV4686 = to_OV4686(sd);
const struct OV4686_mode *mode = OV4686->cur_mode;
u32 val = 1 << (OV4686_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV4686_LANES;
return 0;
}

16
drivers/media/i2c/ov4688.c
View File

@@ -718,7 +718,7 @@ static const struct ov4688_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = ov4688_linear_2688x1520_30fps_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 1920,
.height = 1080,
@@ -732,7 +732,7 @@ static const struct ov4688_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = ov4688_linear_1920x1080_60fps_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -984,19 +984,9 @@ static int ov4688_g_frame_interval(struct v4l2_subdev *sd,
static int ov4688_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov4688 *ov4688 = to_ov4688(sd);
const struct ov4688_mode *mode = ov4688->cur_mode;
u32 val = 1 << (OV4688_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV4688_LANES;
return 0;
}

30
drivers/media/i2c/ov4689.c
View File

@@ -486,7 +486,7 @@ static const struct ov4689_mode supported_modes[] = {
.vts_def = 0x0612,
.reg_list = ov4689_linear_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 2688,
.height = 1520,
@@ -499,10 +499,10 @@ static const struct ov4689_mode supported_modes[] = {
.vts_def = 0x0612,
.reg_list = ov4689_hdr_x2_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
}, {
.width = 2688,
.height = 1520,
@@ -515,10 +515,10 @@ static const struct ov4689_mode supported_modes[] = {
.vts_def = 0x0612,
.reg_list = ov4689_hdr_x3_regs,
.hdr_mode = HDR_X3,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr1
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
.vc[PAD0] = 2,
.vc[PAD1] = 1,//M->csi wr0
.vc[PAD2] = 0,//L->csi wr1
.vc[PAD3] = 2,//S->csi wr2
},
};
@@ -763,19 +763,9 @@ static int ov4689_g_frame_interval(struct v4l2_subdev *sd,
static int ov4689_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov4689 *ov4689 = to_ov4689(sd);
const struct ov4689_mode *mode = ov4689->cur_mode;
u32 val = 1 << (OV4689_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV4689_LANES;
return 0;
}

26
drivers/media/i2c/ov50c40.c
View File

@@ -5750,7 +5750,7 @@ static const struct ov50c40_mode supported_modes_dphy[] = {
.reg_list = ov50c40_10bit_4096x3072_dphy_30fps_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -5768,7 +5768,7 @@ static const struct ov50c40_mode supported_modes_dphy[] = {
.reg_list = ov50c40_10bit_8192x6144_dphy_12fps_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
#ifdef DEBUG
{
@@ -5787,7 +5787,7 @@ static const struct ov50c40_mode supported_modes_dphy[] = {
.reg_list = ov50c40_10bit_4096x3072_dphy_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -5805,7 +5805,7 @@ static const struct ov50c40_mode supported_modes_dphy[] = {
.reg_list = ov50c40_10bit_8192x6144_dphy_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -5822,7 +5822,7 @@ static const struct ov50c40_mode supported_modes_dphy[] = {
.bpp = 10,
.reg_list = ov50c40_10bit_4096x3072_dphy_30fps_nopd_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
#endif
};
@@ -5844,7 +5844,7 @@ static const struct ov50c40_mode supported_modes_cphy[] = {
.reg_list = ov50c40_10bit_4096x3072_cphy_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -5862,7 +5862,7 @@ static const struct ov50c40_mode supported_modes_cphy[] = {
.reg_list = ov50c40_10bit_4096x3072_cphy_30fps_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10,
@@ -5880,7 +5880,7 @@ static const struct ov50c40_mode supported_modes_cphy[] = {
.reg_list = ov50c40_10bit_8192x6144_cphy_12fps_regs,
.hdr_mode = NO_HDR,
.spd = &ov50c40_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -6146,15 +6146,9 @@ static int ov50c40_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov50c40 *ov50c40 = to_ov50c40(sd);
u32 lane_num = ov50c40->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = ov50c40->bus_cfg.bus_type;
config->flags = val;
config->bus.mipi_csi2 = ov50c40->bus_cfg.bus.mipi_csi2;
return 0;
}
@@ -6260,7 +6254,7 @@ static int ov50c40_get_channel_info(struct ov50c40 *ov50c40, struct rkmodule_cha
return -EINVAL;
if (ch_info->index == ov50c40->spd_id && mode->spd) {
ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_1;
ch_info->vc = 1;
ch_info->width = mode->spd->width;
ch_info->height = mode->spd->height;
ch_info->bus_fmt = mode->spd->bus_fmt;

13
drivers/media/i2c/ov5648.c
View File

@@ -1087,16 +1087,11 @@ static int ov5648_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int ov5648_g_mbus_config(struct v4l2_subdev *sd,
static int ov5648_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV5648_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV5648_LANES;
return 0;
}
@@ -1123,7 +1118,6 @@ static const struct v4l2_subdev_core_ops ov5648_core_ops = {
static const struct v4l2_subdev_video_ops ov5648_video_ops = {
.s_stream = ov5648_s_stream,
.g_frame_interval = ov5648_g_frame_interval,
.g_mbus_config = ov5648_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops ov5648_pad_ops = {
@@ -1132,6 +1126,7 @@ static const struct v4l2_subdev_pad_ops ov5648_pad_ops = {
.enum_frame_interval = ov5648_enum_frame_interval,
.get_fmt = ov5648_get_fmt,
.set_fmt = ov5648_set_fmt,
.get_mbus_config = ov5648_g_mbus_config,
};
static const struct v4l2_subdev_ops ov5648_subdev_ops = {

6
drivers/media/i2c/ov5670.c
View File

@@ -1409,12 +1409,8 @@ static int ov5670_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 1 << (OV5670_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV5670_LANES;
return 0;
}

7
drivers/media/i2c/ov5695.c
View File

@@ -1162,13 +1162,8 @@ static int ov5695_enum_frame_interval(struct v4l2_subdev *sd,
static int ov5695_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV5695_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV5695_LANES;
return 0;
}

15
drivers/media/i2c/ov7251.c
View File

@@ -732,7 +732,7 @@ static const struct ov7251_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = ov7251_640x480_120fps_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}
};
@@ -985,19 +985,8 @@ static int ov7251_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct ov7251 *ov7251 = to_ov7251(sd);
const struct ov7251_mode *mode = ov7251->cur_mode;
u32 val = 1 << (OV7251_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV7251_LANES;
return 0;
}

13
drivers/media/i2c/ov7750.c
View File

@@ -948,16 +948,11 @@ static int ov7750_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int ov7750_g_mbus_config(struct v4l2_subdev *sd,
static int ov7750_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV7750_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV7750_LANES;
return 0;
}
@@ -983,7 +978,6 @@ static const struct v4l2_subdev_core_ops ov7750_core_ops = {
static const struct v4l2_subdev_video_ops ov7750_video_ops = {
.s_stream = ov7750_s_stream,
.g_mbus_config = ov7750_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops ov7750_pad_ops = {
@@ -992,6 +986,7 @@ static const struct v4l2_subdev_pad_ops ov7750_pad_ops = {
.enum_frame_interval = ov7750_enum_frame_interval,
.get_fmt = ov7750_get_fmt,
.set_fmt = ov7750_set_fmt,
.get_mbus_config = ov7750_g_mbus_config,
};
static const struct v4l2_subdev_ops ov7750_subdev_ops = {

11
drivers/media/i2c/ov8858.c
View File

@@ -2867,16 +2867,9 @@ static int ov8858_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
if (2 == sensor->lane_num) {
if (2 == sensor->lane_num || 4 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == sensor->lane_num) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->bus.mipi_csi2.num_data_lanes = sensor->lane_num;
} else {
dev_err(&sensor->client->dev,
"unsupported lane_num(%d)\n", sensor->lane_num);

7
drivers/media/i2c/ov9281.c
View File

@@ -1013,13 +1013,8 @@ static int ov9281_enum_frame_interval(struct v4l2_subdev *sd,
static int ov9281_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV9281_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = OV9281_LANES;
return 0;
}

13
drivers/media/i2c/ov9750.c
View File

@@ -932,16 +932,11 @@ static int ov9750_enum_frame_interval(struct v4l2_subdev *sd,
return 0;
}
static int ov9750_g_mbus_config(struct v4l2_subdev *sd,
static int ov9750_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
u32 val = 0;
val = 1 << (OV9750_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2;
config->flags = val;
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = OV9750_LANES;
return 0;
}
@@ -968,7 +963,6 @@ static const struct v4l2_subdev_core_ops ov9750_core_ops = {
static const struct v4l2_subdev_video_ops ov9750_video_ops = {
.s_stream = ov9750_s_stream,
.g_frame_interval = ov9750_g_frame_interval,
.g_mbus_config = ov9750_g_mbus_config,
};
static const struct v4l2_subdev_pad_ops ov9750_pad_ops = {
@@ -977,6 +971,7 @@ static const struct v4l2_subdev_pad_ops ov9750_pad_ops = {
.enum_frame_interval = ov9750_enum_frame_interval,
.get_fmt = ov9750_get_fmt,
.set_fmt = ov9750_set_fmt,
.get_mbus_config = ov9750_g_mbus_config,
};
static const struct v4l2_subdev_ops ov9750_subdev_ops = {

2
drivers/media/i2c/rk628/rk628_bt1120_v4l2.c
View File

@@ -1216,7 +1216,7 @@ static int rk628_bt1120_g_mbus_config(struct v4l2_subdev *sd,
struct v4l2_mbus_config *cfg)
{
cfg->type = V4L2_MBUS_BT656;
cfg->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
cfg->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_HIGH |
V4L2_MBUS_PCLK_SAMPLE_RISING;

19
drivers/media/i2c/rk628/rk628_csi_v4l2.c
View File

@@ -1424,24 +1424,7 @@ static int rk628_csi_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct rk628_csi *csi = to_csi(sd);
cfg->type = V4L2_MBUS_CSI2_DPHY;
cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
switch (csi->csi_lanes_in_use) {
case 1:
cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
break;
case 2:
cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
break;
case 3:
cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
break;
case 4:
cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
break;
default:
return -EINVAL;
}
cfg->bus.mipi_csi2.num_data_lanes = csi->csi_lanes_in_use;
return 0;
}

13
drivers/media/i2c/s5k3l6xx.c
View File

@@ -1076,17 +1076,8 @@ static int s5k3l6xx_enum_frame_interval(struct v4l2_subdev *sd,
static int s5k3l6xx_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
struct v4l2_mbus_config *config)
{
if (2 == S5K3L6XX_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_2_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
} else if (4 == S5K3L6XX_LANES) {
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = V4L2_MBUS_CSI2_4_LANE |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
config->type = V4L2_MBUS_CSI2_DPHY;
config->bus.mipi_csi2.num_data_lanes = S5K3L6XX_LANES;
return 0;
}

14
drivers/media/i2c/s5kjn1.c
View File

@@ -870,7 +870,7 @@ static const struct s5kjn1_mode supported_modes_dphy[] = {
.reg_list = s5kjn1_10bit_4080x3072_dphy_30fps_regs,
.hdr_mode = NO_HDR,
.spd = &s5kjn1_spd,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
@@ -887,7 +887,7 @@ static const struct s5kjn1_mode supported_modes_dphy[] = {
.bpp = 10,
.reg_list = s5kjn1_10bit_8128x6144_dphy_10fps_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -1208,15 +1208,9 @@ static int s5kjn1_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct s5kjn1 *s5kjn1 = to_s5kjn1(sd);
u32 lane_num = s5kjn1->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = s5kjn1->bus_cfg.bus_type;
config->flags = val;
config->bus.mipi_csi2 = s5kjn1->bus_cfg.bus.mipi_csi2;
return 0;
}
@@ -1322,7 +1316,7 @@ static int s5kjn1_get_channel_info(struct s5kjn1 *s5kjn1, struct rkmodule_channe
return -EINVAL;
if (ch_info->index == s5kjn1->spd_id && mode->spd) {
ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_1;
ch_info->vc = 1;
ch_info->width = mode->spd->width;
ch_info->height = mode->spd->height;
ch_info->bus_fmt = mode->spd->bus_fmt;

2
drivers/media/i2c/sc031gs.c
View File

@@ -931,7 +931,7 @@ static int sc031gs_g_mbus_config(struct v4l2_subdev *sd,
struct v4l2_mbus_config *config)
{
config->type = V4L2_MBUS_PARALLEL;
config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
config->bus.parallel.flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
V4L2_MBUS_VSYNC_ACTIVE_LOW |
V4L2_MBUS_PCLK_SAMPLE_FALLING;
return 0;

6
drivers/media/i2c/sc035gs.c
View File

@@ -928,14 +928,10 @@ static int sc035gs_enum_frame_interval(struct v4l2_subdev *sd,
static int sc035gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
struct sc035gs *sc035gs = to_sc035gs(sd);
val = 1 << (sc035gs->cur_mode->lanes - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = sc035gs->cur_mode->lanes;
return 0;
}

6
drivers/media/i2c/sc132gs.c
View File

@@ -1043,14 +1043,10 @@ static int sc132gs_enum_frame_interval(struct v4l2_subdev *sd,
static int sc132gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 0;
struct sc132gs *sc132gs = to_sc132gs(sd);
val = 1 << (sc132gs->cur_mode->lanes - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = sc132gs->cur_mode->lanes;
return 0;
}

25
drivers/media/i2c/sc200ai.c
View File

@@ -619,7 +619,7 @@ static const struct sc200ai_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = sc200ai_linear_10_1920x1080_30fps_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 1920,
.height = 1080,
@@ -633,7 +633,7 @@ static const struct sc200ai_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = sc200ai_linear_10_1920x1080_60fps_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 1920,
.height = 1080,
@@ -647,10 +647,10 @@ static const struct sc200ai_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = sc200ai_hdr_10_1920x1080_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1130,19 +1130,8 @@ static int sc200ai_g_frame_interval(struct v4l2_subdev *sd,
static int sc200ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc200ai *sc200ai = to_sc200ai(sd);
const struct sc200ai_mode *mode = sc200ai->cur_mode;
u32 val = 1 << (SC200AI_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC200AI_LANES;
return 0;
}

9
drivers/media/i2c/sc210iot.c
View File

@@ -252,7 +252,7 @@ static const struct sc210iot_mode supported_modes[] = {
.reg_list = sc210iot_1080p_liner_30fps_settings,
.reg_num = ARRAY_SIZE(sc210iot_1080p_liner_30fps_settings),
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -782,13 +782,8 @@ static int sc210iot_g_frame_interval(struct v4l2_subdev *sd,
static int sc210iot_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc210iot *sc210iot = to_sc210iot(sd);
u32 val = 1 << (SC210IOT_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = (sc210iot->cur_mode->hdr_mode == NO_HDR) ?
val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
config->bus.mipi_csi2.num_data_lanes = SC210IOT_LANES;
return 0;
}

18
drivers/media/i2c/sc2232.c
View File

@@ -352,7 +352,7 @@ static const struct sc2232_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.mipi_freq_idx = 0,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -600,22 +600,8 @@ static int sc2232_g_frame_interval(struct v4l2_subdev *sd,
static int sc2232_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc2232 *sc2232 = to_sc2232(sd);
const struct sc2232_mode *mode = sc2232->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (SC2232_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (SC2232_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC2232_LANES;
return 0;
}

6
drivers/media/i2c/sc2239.c
View File

@@ -858,12 +858,8 @@ static int sc2239_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
static int sc2239_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
u32 val = 1 << (SC2239_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC2239_LANES;
return 0;
}

17
drivers/media/i2c/sc230ai.c
View File

@@ -554,7 +554,7 @@ static const struct sc230ai_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.bpp = 10,
.mipi_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 640,
.height = 480,
@@ -570,7 +570,7 @@ static const struct sc230ai_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.bpp = 10,
.mipi_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -899,19 +899,8 @@ static int sc230ai_g_frame_interval(struct v4l2_subdev *sd,
static int sc230ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc230ai *sc230ai = to_sc230ai(sd);
const struct sc230ai_mode *mode = sc230ai->cur_mode;
u32 val = 1 << (SC230AI_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC230AI_LANES;
return 0;
}

26
drivers/media/i2c/sc2310.c
View File

@@ -583,7 +583,7 @@ static const struct sc2310_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.mipi_freq_idx = 0,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
/* 2 to 1 hdr */
@@ -601,10 +601,10 @@ static const struct sc2310_mode supported_modes[] = {
.hdr_mode = HDR_X2,
.mipi_freq_idx = 1,
.bpp = 10,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -874,22 +874,8 @@ static int sc2310_g_frame_interval(struct v4l2_subdev *sd,
static int sc2310_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc2310 *sc2310 = to_sc2310(sd);
const struct sc2310_mode *mode = sc2310->cur_mode;
u32 val = 0;
if (mode->hdr_mode == NO_HDR)
val = 1 << (SC2310_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode == HDR_X2)
val = 1 << (SC2310_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
V4L2_MBUS_CSI2_CHANNEL_1;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC2310_LANES;
return 0;
}

15
drivers/media/i2c/sc2336.c
View File

@@ -344,7 +344,7 @@ static const struct sc2336_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.xvclk_freq = 24000000,
.link_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
};
@@ -669,20 +669,9 @@ static int sc2336_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc2336 *sc2336 = to_sc2336(sd);
const struct sc2336_mode *mode = sc2336->cur_mode;
u32 val = 1 << (SC2336_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC2336_LANES;
return 0;
}

32
drivers/media/i2c/sc301iot.c
View File

@@ -838,7 +838,7 @@ static const struct SC301IOT_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = SC301IOT_linear_10_2048x1536_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 2048,
.height = 1536,
@@ -852,10 +852,10 @@ static const struct SC301IOT_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = SC301IOT_hdr_10_2048x1536_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
}, {
.width = 1536,
.height = 1536,
@@ -869,7 +869,7 @@ static const struct SC301IOT_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = SC301IOT_linear_10_1536x1536_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}, {
.width = 1536,
.height = 1536,
@@ -883,10 +883,10 @@ static const struct SC301IOT_mode supported_modes[] = {
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = SC301IOT_hdr_10_1536x1536_regs,
.hdr_mode = HDR_X2,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
.vc[PAD0] = 1,
.vc[PAD1] = 0,//L->csi wr0
.vc[PAD2] = 1,
.vc[PAD3] = 1,//M->csi wr2
},
};
@@ -1286,19 +1286,9 @@ static int SC301IOT_g_frame_interval(struct v4l2_subdev *sd,
static int SC301IOT_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct SC301IOT *SC301IOT = to_SC301IOT(sd);
const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
u32 val = 1 << (SC301IOT_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC301IOT_LANES;
return 0;
}

17
drivers/media/i2c/sc3336.c
View File

@@ -476,7 +476,7 @@ static const struct sc3336_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.xvclk_freq = 27000000,
.link_freq_idx = 0,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
},
{
.width = 2304,
@@ -493,7 +493,7 @@ static const struct sc3336_mode supported_modes[] = {
.hdr_mode = NO_HDR,
.xvclk_freq = 24000000,
.link_freq_idx = 1,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD0] = 0,
}
};
@@ -830,20 +830,9 @@ static int sc3336_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad_id,
struct v4l2_mbus_config *config)
{
struct sc3336 *sc3336 = to_sc3336(sd);
const struct sc3336_mode *mode = sc3336->cur_mode;
u32 val = 1 << (SC3336_LANES - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
if (mode->hdr_mode != NO_HDR)
val |= V4L2_MBUS_CSI2_CHANNEL_1;
if (mode->hdr_mode == HDR_X3)
val |= V4L2_MBUS_CSI2_CHANNEL_2;
config->type = V4L2_MBUS_CSI2_DPHY;
config->flags = val;
config->bus.mipi_csi2.num_data_lanes = SC3336_LANES;
return 0;
}

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