shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 12:57:06 +09:00
Code Issues Packages Projects Releases Wiki Activity

osd: add mali-afbc frame reset for g12b

Browse Source 
PD#165090: osd: add mali-afbc frame reset for g12b

Change-Id: If0176807a1a845a1eebb6c53ad05fdff2e5a1654
Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
This commit is contained in:
pengcheng chen
2018-05-12 15:46:26 +08:00
committed by Yixun Lan
parent f1b8fec674
commit 8757969ec1
3 changed files with 40 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/amlogic/media/osd/osd.h
View File

@@ -701,6 +701,7 @@ struct hw_para_s {
u32 vinfo_height;
u32 fb_drvier_probe;
u32 afbc_force_reset;
u32 afbc_regs_backup;
u32 afbc_status_err_reset;
u32 afbc_use_latch;
u32 hwc_enable;

35
drivers/amlogic/media/osd/osd_hw.c
View File

@@ -1528,16 +1528,19 @@ void osd_hw_reset(void)
if ((osd_hw.osd_meson_dev.afbc_type == MALI_AFBC)
&& (reset_bit & HW_RESET_MALI_AFBCD_REGS)) {
/* restore mali afbcd regs */
int i;
u32 addr;
u32 value;
u32 base = VPU_MAFBC_IRQ_MASK;
if (osd_hw.afbc_regs_backup) {
int i;
u32 addr;
u32 value;
u32 base = VPU_MAFBC_IRQ_MASK;
for (i = 0; i < MALI_AFBC_REG_BACKUP_COUNT; i++) {
addr = mali_afbc_reg_backup[i];
value = mali_afbc_backup[addr - base];
VSYNCOSD_IRQ_WR_MPEG_REG(
addr, value);
for (i = 0; i < MALI_AFBC_REG_BACKUP_COUNT;
i++) {
addr = mali_afbc_reg_backup[i];
value = mali_afbc_backup[addr - base];
VSYNCOSD_IRQ_WR_MPEG_REG(
addr, value);
}
}
VSYNCOSD_IRQ_WR_MPEG_REG(VPU_MAFBC_COMMAND, 1);
}
@@ -7086,8 +7089,20 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
MALI_AFBC_32X8_PIXEL << 1 |
MALI_AFBC_SPLIT_ON;
osd_hw.osd_afbcd[idx].afbc_start = 0;
osd_hw.afbc_force_reset = 1;
osd_hw.osd_afbcd[idx].out_addr_id = idx + 1;
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_G12A) {
osd_hw.afbc_force_reset = 1;
osd_hw.afbc_regs_backup = 1;
} else {
osd_hw.afbc_force_reset = 1;
osd_hw.afbc_regs_backup = 0;
data32 = osd_reg_read(MALI_AFBCD_TOP_CTRL);
osd_reg_write(MALI_AFBCD_TOP_CTRL,
data32 | 0x800000);
}
if (idx < osd_hw.osd_meson_dev.osd_count - 1) {
/* TODO: temp set at here,
* need move it to uboot

29
drivers/amlogic/media/osd/osd_rdma.c
View File

@@ -1215,22 +1215,21 @@ int osd_rdma_reset_and_flush(u32 reset_bit)
addr, value);
i++;
}
i = 0;
base = VPU_MAFBC_IRQ_MASK;
while ((reset_bit & HW_RESET_MALI_AFBCD_REGS)
&& (i < MALI_AFBC_REG_BACKUP_COUNT)) {
addr = mali_afbc_reg_backup[i];
value = mali_afbc_backup[addr - base];
wrtie_reg_internal(
addr, value);
i++;
}
if ((reset_bit & HW_RESET_MALI_AFBCD_REGS)
&& ((osd_hw.osd_meson_dev.cpu_id
== __MESON_CPU_MAJOR_ID_G12A) ||
(osd_hw.osd_meson_dev.cpu_id
== __MESON_CPU_MAJOR_ID_G12B)))
if (osd_hw.afbc_regs_backup) {
i = 0;
base = VPU_MAFBC_IRQ_MASK;
while ((reset_bit & HW_RESET_MALI_AFBCD_REGS)
&& (i < MALI_AFBC_REG_BACKUP_COUNT)) {
addr = mali_afbc_reg_backup[i];
value = mali_afbc_backup[addr - base];
wrtie_reg_internal(
addr, value);
i++;
}
}
if ((osd_hw.osd_meson_dev.afbc_type == MALI_AFBC) &&
(osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE))
wrtie_reg_internal(VPU_MAFBC_COMMAND, 1);
if (item_count < 500)