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arm64: dts: rockchip: rk3399-android-next: add isp

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Change-Id: I8db91aae4dfd9c1b1ad39adb1e8377aba0c34fca
Signed-off-by: dalong.zhang <dalon.zhang@rock-chips.com>
This commit is contained in:
dalong.zhang
2016-11-24 21:14:28 +08:00
parent 0aa1636f87
commit 8768af65f5
1 changed files with 141 additions and 0 deletions
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141
arch/arm64/boot/dts/rockchip/rk3399-android-next.dtsi
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@@ -134,6 +134,86 @@
rockchip,adc_value = <450>;
};
};
isp0: isp@ff910000 {
compatible = "rockchip,rk3399-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
clocks =
<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
<&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
<&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
<&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
clock-names =
"clk_cif_out", "clk_cif_pll",
"pclk_dphytxrx", "pclk_dphy_ref",
"aclk_isp0_noc", "aclk_isp0_wrapper",
"hclk_isp0_noc", "hclk_isp0_wrapper",
"clk_isp0", "pclk_dphyrx";
pinctrl-names =
"cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
"isp_mipi_fl_prefl", "isp_flash_as_gpio",
"isp_flash_as_trigger_out";
pinctrl-0 = <&cif_clkout>;
pinctrl-1 = <&isp_dvp_d0d7>;
pinctrl-2 = <&cif_clkout>;
pinctrl-3 = <&isp_prelight>;
pinctrl-4 = <&isp_flash_trigger_as_gpio>;
pinctrl-5 = <&isp_flash_trigger>;
rockchip,isp,mipiphy = <2>;
rockchip,isp,cifphy = <1>;
rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
rockchip,isp,iommu-enable = <1>;
power-domains = <&power RK3399_PD_ISP0>;
iommus = <&isp0_mmu>;
status = "disabled";
};
isp1: isp@ff920000 {
compatible = "rockchip,rk3399-isp", "rockchip,isp";
reg = <0x0 0xff920000 0x0 0x4000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
clocks =
<&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
<&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
<&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
<&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
<&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
<&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
<&cru SCLK_MIPIDPHY_CFG>;
clock-names =
"aclk_isp1_noc", "aclk_isp1_wrapper",
"hclk_isp1_noc", "hclk_isp1_wrapper",
"clk_isp1", "clk_cif_out",
"clk_cif_pll", "pclk_dphytxrx",
"pclk_dphy_ref", "pclk_isp1",
"pclk_dphyrx", "pclk_mipi_dsi",
"mipi_dphy_cfg";
pinctrl-names =
"cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
"isp_mipi_fl_prefl", "isp_flash_as_gpio",
"isp_flash_as_trigger_out";
pinctrl-0 = <&cif_clkout>;
pinctrl-1 = <&isp_dvp_d0d7>;
pinctrl-2 = <&cif_clkout>;
pinctrl-3 = <&isp_prelight>;
pinctrl-4 = <&isp_flash_trigger_as_gpio>;
pinctrl-5 = <&isp_flash_trigger>;
rockchip,isp,mipiphy = <2>;
rockchip,isp,cifphy = <1>;
rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
rockchip,isp,iommu-enable = <1>;
power-domains = <&power RK3399_PD_ISP1>;
iommus = <&isp1_mmu>;
status = "disabled";
};
};
&mipi_dsi {
@@ -227,3 +307,64 @@
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
&pinctrl {
isp {
cif_clkout: cif-clkout {
rockchip,pins =
/*cif_clkout*/
<2 11 RK_FUNC_3 &pcfg_pull_none>;
};
isp_dvp_d0d7: isp-dvp-d0d7 {
rockchip,pins =
/*cif_data0*/
<2 0 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data1*/
<2 1 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data2*/
<2 2 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data3*/
<2 3 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data4*/
<2 4 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data5*/
<2 5 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data6*/
<2 6 RK_FUNC_3 &pcfg_pull_none>,
/*cif_data7*/
<2 7 RK_FUNC_3 &pcfg_pull_none>,
/*cif_sync*/
<2 8 RK_FUNC_3 &pcfg_pull_none>,
/*cif_href*/
<2 9 RK_FUNC_3 &pcfg_pull_none>,
/*cif_clkin*/
<2 10 RK_FUNC_3 &pcfg_pull_none>;
};
isp_shutter: isp-shutter {
rockchip,pins =
/*SHUTTEREN*/
<1 1 RK_FUNC_1 &pcfg_pull_none>,
/*SHUTTERTRIG*/
<1 0 RK_FUNC_1 &pcfg_pull_none>;
};
isp_flash_trigger: isp-flash-trigger {
/*ISP_FLASHTRIGOU*/
rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
};
isp_prelight: isp-prelight {
/*ISP_PRELIGHTTRIG*/
rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
};
isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
/*ISP_FLASHTRIGOU*/
rockchip,pins =
<0 17 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};