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arm64: dts: rockchip: add cif nodes for rk3368

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Change-Id: Ibe12b5eeac5a9fd929e22592a480352057560a6e
Signed-off-by: Peng Zhou <benjo.zhou@rock-chips.com>
This commit is contained in:
Peng Zhou
2017-10-31 09:34:11 +08:00
committed by Tao Huang
parent 798ec1bde5
commit 87ee4d5097
1 changed files with 34 additions and 14 deletions
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48
arch/arm64/boot/dts/rockchip/rk3368.dtsi
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@@ -1333,20 +1333,10 @@
"pclk_dphyrx", "clk_vio0_noc";
pinctrl-names =
"default", "isp_dvp8bit2", "isp_dvp10bit",
"isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
"isp_mipi_fl", "isp_mipi_fl_prefl",
"isp_flash_as_gpio", "isp_flash_as_trigger_out";
pinctrl-0 = <&cif_clkout>;
pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
pinctrl-6 = <&cif_clkout>;
pinctrl-7 = <&cif_clkout &isp_prelight>;
pinctrl-8 = <&isp_flash_trigger_as_gpio>;
pinctrl-9 = <&isp_flash_trigger>;
"isp_mipi_fl_prefl", "isp_flash_as_gpio", "isp_flash_as_trigger_out";
pinctrl-0 = <&isp_prelight>;
pinctrl-1 = <&isp_flash_trigger_as_gpio>;
pinctrl-2 = <&isp_flash_trigger>;
rockchip,isp,mipiphy = <2>;
rockchip,isp,cifphy = <1>;
rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
@@ -1432,6 +1422,36 @@
status = "disabled";
};
cif: cif@ff950000 {
compatible = "rockchip,cif";
reg = <0x0 0xff950000 0x0 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
<&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
"cif0_in", "cif0_out";
resets = <&cru SRST_VIP>;
reset-names = "rst_cif";
pinctrl-names = "cif_pin_all";
pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
rockchip,grf = <&grf>;
power-domains = <&power RK3368_PD_VIO>;
status = "disabled";
};
vip_mmu: iommu@ff950800{
compatible = "rockchip,iommu";
reg = <0x0 0xff950800 0x0 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vip_mmu";
clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>;
clock-names = "aclk", "hclk";
rk_iommu,disable_reset_quirk;
#iommu-cells = <0>;
power-domains = <&power RK3368_PD_VIO>;
status = "disabled";
};
dsi: dsi@ff960000 {
compatible = "rockchip,rk3368-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;