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media: i2c: rk628: fix no display because clear avmute is not received

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Signed-off-by: Chen Shunqing <csq@rock-chips.com>
Change-Id: Iede1b6f196747eea5864b853c28b1cccaa7baa6c
This commit is contained in:
Chen Shunqing
2024-07-26 10:01:55 +08:00
committed by Tao Huang
parent d56a729dca
commit 8826fbcc1d
3 changed files with 14 additions and 0 deletions
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5
drivers/media/i2c/rk628/rk628_bt1120_v4l2.c
View File

@@ -617,6 +617,11 @@ static void enable_stream(struct v4l2_subdev *sd, bool en)
}
rk628_hdmirx_vid_enable(sd, true);
enable_bt1120tx(sd);
rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_PDEC_CTRL,
GCPFORCE_CLRAVMUTE_MASK, GCPFORCE_CLRAVMUTE(1));
rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_PDEC_CTRL,
GCPFORCE_CLRAVMUTE_MASK, GCPFORCE_CLRAVMUTE(0));
} else {
rk628_i2c_write(bt1120->rk628, GRF_SCALER_CON0, SCL_EN(0));
rk628_hdmirx_vid_enable(sd, false);

5
drivers/media/i2c/rk628/rk628_csi_v4l2.c
View File

@@ -911,6 +911,11 @@ static void enable_stream(struct v4l2_subdev *sd, bool en)
rk628_csi_enable_csi_interrupts(sd, true);
}
rk628_hdmirx_vid_enable(sd, true);
rk628_i2c_update_bits(csi->rk628, HDMI_RX_PDEC_CTRL,
GCPFORCE_CLRAVMUTE_MASK, GCPFORCE_CLRAVMUTE(1));
rk628_i2c_update_bits(csi->rk628, HDMI_RX_PDEC_CTRL,
GCPFORCE_CLRAVMUTE_MASK, GCPFORCE_CLRAVMUTE(0));
} else {
if (csi->plat_data->tx_mode == CSI_MODE) {
rk628_csi_enable_csi_interrupts(sd, false);

4
drivers/media/i2c/rk628/rk628_hdmirx.h
View File

@@ -243,6 +243,8 @@
#define PFIFO_STORE_GCP(x) UPDATE(x, 17, 17)
#define PFIFO_STORE_ACR_MASK BIT(16)
#define PFIFO_STORE_ACR(x) UPDATE(x, 16, 16)
#define GCPFORCE_CLRAVMUTE_MASK BIT(14)
#define GCPFORCE_CLRAVMUTE(x) UPDATE(x, 14, 14)
#define GCPFORCE_SETAVMUTE_MASK BIT(13)
#define GCPFORCE_SETAVMUTE(x) UPDATE(x, 13, 13)
#define PDEC_BCH_EN_MASK BIT(0)
@@ -258,6 +260,8 @@
#define DVI_DET BIT(28)
#define HDMI_RX_PDEC_GCP_AVMUTE (HDMI_RX_BASE + 0x0380)
#define PKTDEC_GCP_CD_MASK GENMASK(7, 4)
#define PKTDEC_GCP_SETAVMUTE_MASK GENMASK(1, 1)
#define PKTDEC_GCP_CLRAVMUTE_MASK GENMASK(0, 0)
#define HDMI_RX_PDEC_AVI_HB (HDMI_RX_BASE + 0x03a0)
#define HDMI_RX_PDEC_AVI_PB (HDMI_RX_BASE + 0x03a4)
#define VID_IDENT_CODE_VIC7 BIT(31)