rk32 edp: add debugfs support

add bist test support

drivers/video/rockchip/transmitter/dpcd_edid.h

@@ -36,6 +36,7 @@
 #define DPCD_TRAINING_SCORE_LANE1                       0x209
 #define DPCD_TRAINING_SCORE_LANE2                       0x20a
 #define DPCD_TRAINING_SCORE_LANE3                       0x20b
+#define DPCD_SYMBOL_ERR_CONUT_LANE0			0x210
 #define DPCD_SINK_POWER_STATE				0x0600
 
 /* DPCD_ADDR_MAX_LANE_COUNT */

drivers/video/rockchip/transmitter/rk32_dp.c

@@ -31,6 +31,12 @@
 #include <linux/of.h>
 #endif
 
+#if defined(CONFIG_DEBUG_FS)
+#include <linux/fs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#endif
+
 //#define EDP_BIST_MODE
 
 static struct rk32_edp *rk32_edp;
@@ -1019,8 +1025,9 @@ static int rk32_edp_config_video(struct rk32_edp *edp,
 	rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
+#ifndef EDP_BIST_MODE
 	rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
-
+#endif
 	/* Disable video mute */
 	rk32_edp_enable_video_mute(edp, 0);
 
@@ -1162,15 +1169,15 @@ static int rk32_edp_enable(void)
 
 	rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 	rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
+	rk32_edp_init_video(edp);
 
 #ifdef EDP_BIST_MODE
 	rk32_edp_bist_cfg(edp);
-#else
-	rk32_edp_init_video(edp);
+#endif
 	ret = rk32_edp_config_video(edp, &edp->video_info);
 	if (ret)
 		dev_err(edp->dev, "unable to config video\n");
-#endif
+
 	return ret;
 
 
@@ -1194,6 +1201,80 @@ static struct rk_fb_trsm_ops trsm_edp_ops = {
 	.enable = rk32_edp_enable,
 	.disable = rk32_edp_disable,
 };
+
+
+#if defined(CONFIG_DEBUG_FS)
+
+static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
+{
+	int i = 0;
+	unsigned char buf[12];
+	struct rk32_edp *edp = s->private;
+	if (!edp) {
+		dev_err(edp->dev, "no edp device!\n");
+		return -ENODEV;
+	}
+	
+	
+	rk32_edp_read_bytes_from_dpcd(edp,
+			DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
+	for (i=0;i< 12;i++) {
+		seq_printf(s,"0x%02x>>0x%02x\n",0x210 + i, buf[i]);
+	}
+	return 0;
+}
+
+static int edp_edid_debugfs_show(struct seq_file *s, void *v)
+{
+	int i = 0;
+	unsigned char buf[12];
+	struct rk32_edp *edp = s->private;
+	if (!edp) {
+		dev_err(edp->dev, "no edp device!\n");
+		return -ENODEV;
+	}
+	seq_printf(s,"edid");
+	return 0;
+}
+
+static int edp_reg_debugfs_show(struct seq_file *s, void *v)
+{
+	int i = 0;
+	struct rk32_edp *edp = s->private;
+	if (!edp) {
+		dev_err(edp->dev, "no edp device!\n");
+		return -ENODEV;
+	}
+
+	for (i = 0; i < 0x284; i++) {
+		if (!(i%4))
+			seq_printf(s, "\n%08x:  ", i*4);
+		seq_printf(s, "%08x ", readl(edp->regs + i*4));
+	}
+	return 0;
+}
+
+
+#define EDP_DEBUG_ENTRY(name) \
+static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
+{ \
+	return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
+} \
+\
+static const struct file_operations edp_##name##_debugfs_fops = { \
+	.owner = THIS_MODULE, \
+	.open = edp_##name##_debugfs_open, \
+	.read = seq_read, \
+	.llseek = seq_lseek, \
+	.release = single_release, \
+}
+
+EDP_DEBUG_ENTRY(dpcd);
+EDP_DEBUG_ENTRY(edid);
+EDP_DEBUG_ENTRY(reg);
+
+#endif
+
 static int rk32_edp_probe(struct platform_device *pdev)
 {
 	struct rk32_edp *edp;
@@ -1275,6 +1356,20 @@ static int rk32_edp_probe(struct platform_device *pdev)
 	rk32_edp_clk_disable(edp);
 	rk32_edp = edp;
 	rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
+#if defined(CONFIG_DEBUG_FS)
+	edp->debugfs_dir = debugfs_create_dir("edp", NULL);
+	if (IS_ERR(edp->debugfs_dir)) {
+		dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
+	} else {
+		debugfs_create_file("dpcd", S_IRUSR,edp->debugfs_dir,
+					edp, &edp_dpcd_debugfs_fops);
+		debugfs_create_file("edid", S_IRUSR,edp->debugfs_dir,
+					edp, &edp_edid_debugfs_fops);
+		debugfs_create_file("reg", S_IRUSR,edp->debugfs_dir,
+					edp, &edp_reg_debugfs_fops);
+	}
+	
+#endif
 	dev_info(&pdev->dev, "rk32 edp driver probe success\n");
 
 	return 0;

drivers/video/rockchip/transmitter/rk32_dp.h

@@ -522,6 +522,7 @@ struct rk32_edp {
 	struct rk_screen	screen;
 	struct fb_monspecs      specs;
 	bool 			clk_on;
+	struct dentry *debugfs_dir;
 };
 
 

drivers/video/rockchip/transmitter/rk32_dp_reg.c

@@ -1064,8 +1064,6 @@ int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp)
 	writel(val, edp->regs + SYS_CTL_2);
 
 	val = readl(edp->regs + SYS_CTL_2);
-	dev_dbg(edp->dev, "wait SYS_CTL_2.\n");
-
 	if (val & CHA_STA) {
 		dev_dbg(edp->dev, "Input stream clk is changing\n");
 		return -EINVAL;
@@ -1136,11 +1134,13 @@ int rk32_edp_bist_cfg(struct rk32_edp *edp)
 	y_total = screen->mode.upper_margin + screen->mode.lower_margin +
 			screen->mode.yres + screen->mode.vsync_len;
 	x_act = screen->mode.xres;
+
 	rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 	rk32_edp_set_video_color_format(edp, video_info->color_depth,
 					video_info->color_space,
 					video_info->dynamic_range,
 					video_info->ycbcr_coeff);
+
 	val = y_total & 0xff;
 	writel(val, edp->regs + TOTAL_LINE_CFG_L);
 	val = (y_total >> 8);
@@ -1176,19 +1176,17 @@ int rk32_edp_bist_cfg(struct rk32_edp *edp)
 	val = screen->mode.left_margin  >> 8;
 	writel(val, edp->regs + HB_PORCHH_REG);
 
-	val = BIST_EN;
+	val = BIST_EN | BIST_WH_64 | BIST_TYPE_COLR_BAR;
 	writel(val, edp->regs + VIDEO_CTL_4);
 
 #ifndef CONFIG_RK_FPGA
-	val = (GRF_EDP_BIST_EN << 16) | GRF_EDP_BIST_EN;
-	writel_relaxed(val,RK_GRF_VIRT + RK3288_GRF_SOC_CON8);
+	//val = (GRF_EDP_BIST_EN << 16) | GRF_EDP_BIST_EN;
+	//writel_relaxed(val,RK_GRF_VIRT + RK3288_GRF_SOC_CON8);
 #endif
 
-
 	val = readl(edp->regs + VIDEO_CTL_10);
 	val &= ~F_SEL;
 	writel(val, edp->regs + VIDEO_CTL_10);
-	
 	return 0;
 	
 }