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clk/rockchip: rk3288: Add support for sclk_testout

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Change-Id: Ibd521712a6517300984db4199ac0164a499dc0f7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Wyon Bi
2020-11-05 16:53:48 +08:00
committed by Tao Huang
parent 485bbe0375
commit 88873a50fa
2 changed files with 14 additions and 0 deletions
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12
drivers/clk/rockchip/clk-rk3288.c
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@@ -221,6 +221,12 @@ PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
PNAME(mux_testout_src_p) = { "aclk_peri", "armclk", "aclk_vio0", "ddrphy",
"aclk_vcodec", "aclk_gpu", "sclk_rga", "aclk_cpu",
"xin24m", "xin27m", "xin32k", "clk_wifi",
"dclk_vop0", "dclk_vop1", "sclk_isp_jpe",
"sclk_isp" };
PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
"sclk_otgphy0_480m" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
@@ -575,6 +581,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
RK3288_CLKGATE_CON(2), 7, GFLAGS),
MUX(SCLK_TESTOUT_SRC, "sclk_testout_src", mux_testout_src_p, 0,
RK3288_MISC_CON, 8, 4, MFLAGS),
COMPOSITE_NOMUX(SCLK_TESTOUT, "sclk_testout", "sclk_testout_src", 0,
RK3288_CLKSEL_CON(2), 8, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 15, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
RK3288_CLKGATE_CON(2), 8, GFLAGS),

2
include/dt-bindings/clock/rk3288-cru.h
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@@ -91,6 +91,8 @@
#define SCLK_MAC_PLL 150
#define SCLK_MAC 151
#define SCLK_MACREF_OUT 152
#define SCLK_TESTOUT_SRC 153
#define SCLK_TESTOUT 154
#define DCLK_VOP0 190
#define DCLK_VOP1 191